#973 enum with base type of "logic" does not compile

[Neil Turton]

Icarus Verilog fails to compile the following code (also attached):

typedef enum logic
{
MODE_FAST,
MODE_ACCURATE
} mode_t;

The error is:
rtl/iv_error1.sv:2: syntax error
rtl/iv_error1.sv:1: error: Syntax error in typedef clause.

According to IEEE 1800-2012

Section 6.8:
integer_vector_type ::= bit | logic | reg

Section 6.19:
enum_base_type :=
[...]
| integer_vector_type [ signing ] [ packed_dimension ]

Addind a dimension is a work-around:

typedef enum logic [0:0]
{
MODE_FAST,
MODE_ACCURATE
} mode_t;

[Martin Whitaker]

I've pushed a fix for this to the master branch on GitHub.