Icarus Verilog / Bugs / #957 No support for SV compilation unit classes, tasks or functions

#957 No support for SV compilation unit classes, tasks or functions

Milestone: devel

Status: closed-fixed

Owner: Stephen Williams

Labels: None

Priority: 5

Updated: 2014-10-02

Created: 2014-09-11

Creator: Cary R.

Private: No

SystemVerilog has added support for classes, tasks and functions to be defined in the compilation unit scope. We currently have messages that this is not supported, but many pieces of SystemVerilog code use this feature (mostly classes). My assumption is that adding support for classes in the compilation unit scope will add most of what is needed to add functions and tasks so I am grouping them all together.

Attached are code examples that run correctly on other simulators.

3 Attachments

sv_root_class.v

sv_root_func.v

sv_root_task.v

Discussion

Stephen Williams - 2014-09-25

The sv_root_class.v function works in the current (2014-09-24) git master. I've added the test to the ivtest suite.

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Stephen Williams - 2014-09-25

assigned_to: Stephen Williams
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Stephen Williams - 2014-10-02

This is now fixed in git master, as of 2014-10-02.

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Stephen Williams - 2014-10-02

status: open --> closed-fixed
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No support for SV compilation unit classes, tasks or functions

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#957 No support for SV compilation unit classes, tasks or functions

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