#80 addition expression width problem

[Anonymous]

I compiled 0.8 from the CVS repository using the following commands:

cvs -d :pserver:cvs@icarus.com:/home/demon/anoncvs login
cvs -d :pserver:cvs@icarus.com:/home/demon/anoncvs get -r v0_8-
branch verilog
cd verilog
. autoconf.sh
./configure
make
make install

then I ran the attached test case using:

iverilog add_test.v
vvp a.out

and it failed.

This test works with other Verilog compilers. Moreover, the code
illustrated synthesizes as expected with several synthesis tools and the
code generated by those synthesis tools simulates as expected with
other Verilog compilers.

I also compiled the latest code from the HEAD of the CVS repository
too. This test likewise failed.

Thanks.

[Nobody/Anonymous]

test to illustrate adding problem

[Stephen Williams]

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It looks in the first glance like "ptr + size" is overflowing
in your example. I'll look at this first in the devel branch
so I've set the group to devel.

Note to self: I think this should be fixed in 0.8 as well,
so don't close it until it is fixed there as well.

[Stephen Williams]

Attachments from 1572756

[Nobody/Anonymous]

Logged In: NO

In the tarball, add_test.tar.gz is a test called add_test.v (not to be confused
with the other test called add_test.v) that includes the following statement:

answer = (a + b + 0) >> 1;

which is incorrectly processed.

The problem is that the unsized constant 0 is being treated as a 16 bit
number instead of the 32 bit number that it should be. I have observed this
using:

iverilog -tstub add_test.v

The IEEE Verilog standard states:

"The number of bits that make up an unsized number (which is a simple
decimal number or a number without the size specification) shall be at least
32."

When this statement is written as:

answer = (a + b + 32'd0) >> 1;

the test works as expected. Therefore, I expect the fix is pretty easy.

Thanks.

[Stephen Williams]

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user_id=97566

pr1570635.v and pr1570635b.v have been extracted from the attached examples
and added to the ivtest regression test suite.

[Stephen Williams]

Patch for devel snapshot 20061009

[Stephen Williams]

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user_id=97566

the attached patch applies to the snapshot 20061009 and fixes both the expression width
cases attached. It is also available in the devel trunk of the CVS repository. This closes the
PR for the devel trunk.

I've changed the group to v0.8 to remind me to look into a fix for this in the v0.8 branch
as well.

[Nobody/Anonymous]

Logged In: NO

Thanks!

[Cary R.]

We have released a new stable version of Icarus Verilog (V0.9) that for normal usage replaces the version this report was filed against (V0.8). The reported bug does not exist in the V0.9 release and V0.8 will no longer be supported. We are closing this report and suggest that you upgrade to V0.9 as soon as possible.