In this example, vcs halts but iverilog does not (it spins forever).
= compilation and running
(a) iverilog (no flags, v0.9.2)
(b) vcs (-full64, D-2009.12)
Compiler version D-2009.12_Full64; Runtime version D-2009.12_Full64; Feb 14 13:14 2010
x = 13
The structure of the always block is: always Stmt, with Stmt = @(x) Stmt', with Stmt' = begin x = x + 1; end . It seems that iverilog is "fast forwarding" the execution of Stmt, resensitising it, before the completion of Stmt', causing it to loop forever.