#77 syntax error in produced vvp file

[xeb]

Hi.
I am using iverilog-0.8.2 on 64bit gentoo os (pentium4(em64t)).
After successful compilation of project by iverilog (there are only
warnings about "leaving bits of the port unconnected") vvp say:
./test:2317: syntax error.

there is some contens of produced file:

#! /usr/bin/vvp
:vpi_time_precision - 11;
:vpi_module "system";
S_0x910070 .scope module, "reg_int_sim" "reg_int_sim";
.timescale -9;
V_$0x946ed0 .net "CPU_rd_addr", 5, 0, C<0>, C<0>, C<0>, C<0>,
C<0>, C<0>;
V_$0x94fa80 .net "CPU_rd_apply", 0, 0, C<0>;
............
E_0x99ddd0 .event/or E_0x99ddd0/0, E_0x99ddd0/1, E_0x99ddd0/2,
E_0x99ddd0/3;
S_0x676f90 .scope module, "U_Rx_RMON_dpram" "RMON_dpram",
S_0x66c9f0;
.timescale 0;
L_0xa52210 .functor BUFZ (-1863462912), V_$0xaa5420[0], C<0>,
C<0>, C<0>;
V_$0x81a580 .net "Addra", 5, 0, V_$0x99de90[0], V_$0x99de90[1],
V_$0x99de90[2], V_$0x99de90[3], V_$0x99de90[4],
V_$0x99de90[5];
V_$0x9eafb0 .net "Addrb", 5, 0, V_$0x99de90[0], V_$0x99de90[1],
V_$0x99de90[2],
..........

line 2317: L_0xa52210 .functor BUFZ (-1863462912),
V_$0xaa5420[0], C<0>, C<0>, C<0>;

[xeb]

produced file with syntax error

[Stephen Williams]

Logged In: YES
user_id=97566

Is there any chance you can attach Verilog source that causes
this problem to happen? It appears that the problem is the
negative value for the delay in the BUFZ functor. That
functor represents a continuous assign to Clkb in the
RMON_dpram module.

[xeb]

Logged In: YES
user_id=1523411

Seems it is: assign #2 Clkb=Clk;

source code:

module RMON_dpram(
Reset ,
Clk ,
//port-a for Rmon
Addra,
Dina,
Douta,
Wea,
//port-b for CPU
Addrb,
Doutb
);

input Reset ;
input Clk ;
//port-a for Rmon
input [5:0] Addra;
input [31:0] Dina;
output [31:0] Douta;
input Wea;
//port-b for CPU
input [5:0] Addrb;
output [31:0] Doutb;
//
******************************************************************************
//internal signals
//
******************************************************************************

wire Clka;
wire Clkb;
assign Clka=Clk;
assign #2 Clkb=Clk;
//
******************************************************************************

duram #(32,6,"M4K") U_duram(
.data_a (Dina ),
.data_b (32'b0 ),
.wren_a (Wea ),
.wren_b (1'b0 ),
.address_a (Addra ),
.address_b (Addrb ),
.clock_a (Clka ),
.clock_b (Clkb ),
.q_a (Douta ),
.q_b (Doutb ));

endmodule

[Stephen Williams]

Logged In: YES
user_id=97566

The code you attached is not complete enough for me to
replicate the problem. There is no duram module, and when
I comment out the instantiation of that module, I do not
see the symptom. Assign with constant delays works in
general, so there is something more to your problem then
simply that line of code.

Can you attach a compilable file that demonstrate the bug?
Thanks,

[xeb]

Logged In: YES
user_id=1523411

Full source code.

[xeb]

Full source code

[Stephen Williams]

Logged In: YES
user_id=97566

This was caused by a precision overflow, which was in turn
caused by inconsistent use of timescale. Try using the
-Wtimescale flag on the iverilog command line, and it will
tell you about missing timescale settings.

Also, the attached patch detects certain delay precision
overflows and prints an error message.

Note that this is a limitation of the 0.8 branch. The devel
tree should relax this precision restriction, although in
this case I think you'll be glad it's caught as an error.

Thanks by the way for the source that allowed me to repeat
the problem.

[Stephen Williams]

Patch fot 0.8.2 to add delay precision error message