#75 wire array causes invalid module item syntax error

[thiede]

verilog-20060809/bin/iverilog test.v
test.v:12: syntax error
test.v:12: error: invalid module item.

svls56:data> more test.v

module test ();
wire [1:0] b [0:2];
endmodule

[thiede]

[Stephen Williams]

Logged In: YES
user_id=97566
Originator: NO

This bug is fixed by the current CVS as of 16 Jan 2007. The changes are far too
extensive to allow for posting a patch here, to to get the fix, get a snapshot that
is later then this CVS commit, or get the code directly from CVS.

Also, the pr1565544.v test is added to the ivtest regression test suite.

[thiede]

Logged In: YES
user_id=1606747
Originator: YES

hmm, cvs as of 9:40 Jan 16 doesn't compile under cygwin.

I get

ivl.exp:fake:(.edata+0x140): undefined reference to `_ivl_lpm_memory'
make: *** [ivl.exe] Error 1

[Stephen Williams]

Logged In: YES
user_id=97566
Originator: NO

The problem here is that ivl.def didn't get edited to remove the half-dozen
functions that I removed as part of this process. Remove "ivl_lpm_memory"
from your ivl.def file, and try again until it links, then send me your
completed ivl.def and I'll check it and commit it.