Icarus Verilog / Bugs / #626 VHDL Declaring logic in scope type

#626 VHDL Declaring logic in scope type

Milestone: devel

Status: open

Owner: nobody

Labels: Verilog compiler bug (683)

Priority: 4

Updated: 2009-01-21

Created: 2009-01-21

Creator: thiede

Private: No

performance bottleneck:
iverilog test.v takes 2 min total to create a.out
iverilog -pdebug=1 -tvhdl test.v spends 8 min in "Declaring logic in scope type"
No single module sticks out.

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thiede - 2009-01-21

low priority, "just" a performance issue

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thiede - 2009-01-21

priority: 5 --> 4
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VHDL Declaring logic in scope type

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#626 VHDL Declaring logic in scope type

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