#573 real register in always statement not supported

[Tom Sheffler]

Real registers behave just like logic registers with respect to new values and how update events are reported in some Verilog simulators. The following example runs in some implementations of Verilog, but does not parse in Icarus.

/*
* Some simple tests involving real registers.
*/

module top;

real r1;
real r2;

initial
begin
r1 = 1.0;
r2 = 2.0;
#10 r1 = 3.0;
#10 r2 = 4.0;
end

always @(r1)
$display("%t The value of R1 is: %f", $time, r1);

always @(r2)
$display("%t The value of R2 is: %f", $time, r2);

endmodule

Here is a fragment of example output from a simulator that supports running this:

Begin simulation:
Approximately 417620 bytes storage allocated (excluding udps).

10 The value of R1 is: 3.000000
20 The value of R2 is: 4.000000
0 simulation events and 0 declarative immediate assigns processed.
12 behavioral statements executed (7 procedural suspends).
Times (in sec.): Translate 0.0, load/optimize 0.1, simulation 0.1.
Approximately 417620 bytes storage allocated (excluding udps).
No errors and no warnings.

[Cary R.]

This works correctly using the 0.9.devel version of Icarus. Real is only minimally supported in V0.8. Given our focus on getting V0.9 out (no we don't have an exact date) this will likely not be fixed in V0.8. V0.9.devel is a much more capable simulator and is quite stable. If you are not using the synthesis that comes with V0.8 we recommend using v0.9.devel if possible. You can grab a development snapshot from http://www.icarus.com/eda/verilog/ or if you want the cutting edge look at the documentation on how to get this using git.

I'm going to close this report since we do not plan to implement this functionality in V0.8.