#557 Constant Wire Bug

[Şadi Çağatay Öztürk]

Hi,

Details of the bug follows:

<code>
module bug02_constantWire;

//a constant signal wire
wire[31:0] x= -805306367; //32'hd0000001

reg[31:0] y;

initial begin
y= -805306367;
//BUG HERE:
// prints x=50000001, y=d0000001; should print x=d0000001, y=d0000001
#3 $display("x=%0h, y=%0h; expected output x=d0000001, y=d0000001",x, y);
end

endmodule

</code>

Best Regards,

Sadi.

[Şadi Çağatay Öztürk]

[Şadi Çağatay Öztürk]

The data that I assign to x is -805306367 which is 32'hd0000001 in hex. It seems to me that while the "-805306367" is parsed the most significant bit of the number is lost/omitted. I think this because if I write x = -32d805306367 , it works fine... I first suspected that there is a miscalculation made in the 2's complement operation for constant wire assignments but since -32d805306367 works fine that is not the case...

[Cary R.]

FYI this also works in the development version.

[Şadi Çağatay Öztürk]

Ok. Thank you very much for the feedback.

[Cary R.]

Lets keep this open until we decide if we are going to fix this in V0.8 or not. Probably not, but if the bug is closed it will certainly not get fixed!

[Şadi Çağatay Öztürk]

Oh ok :). Any release date for the 0.9 version? :D

[Cary R.]

All we can say is we are working on it. Even though it is in development the snapshots and usually the latest head in git are quite stable.

[Cary R.]

I looked at this briefly and the problem is that the compiler is generating incorrect code. I will see if I can track this down and fix the problem.

[Cary R.]

This is a signed problem in V0.8 it is not keeping that this is a signed value in the negate operator and even if it did the continuous assignment is not doing a signed pad. This is too big of a change for V0.8. If you need to use V0.8 your workaround is the best solution.