#556 Inner Block Decleration Bug

[Şadi Çağatay Öztürk]

Hi,

Details of the bug follows:

<code>
module bug01_innerBlockDeclaration;

task t1;
begin: t1Body
integer i;
for (i=0;i<2;i=i+1) begin: b0
// BUG HERE
//displays
//i=0 a[i]=1000 x=1000
//i=1 a[i]=1001 x=1000

    //it should display: i=1 a\[i\]=1001 x=1001  for the second line
    //Bug goes away if "integer x" declaration is moved to the outer block
    integer x;
    x=a\[i\]; $display\("i=%0d a\[i\]=%0d x=%0d; expecting: \(x==a\[i\]\)",i,a\[i\],x\);
end

end
endtask

integer a[0:1];

initial begin
a[0]=1000;
a[1]=1001;
t1;
end

endmodule
</code>

Best Regards,

Sadi.

[Şadi Çağatay Öztürk]

Verilog module with Inner Block Decleration Bug

[Şadi Çağatay Öztürk]

File Added: bug01_innerBlockDeclaration.v

[Cary R.]

FYI this works correctly in the development version (0.9.devel)

[Şadi Çağatay Öztürk]

Ok. Thank you very much for the feedback.

[Cary R.]

Which version of 0.8 are you using? This appears to be fixed in the latest 0.8 version from git. The other two you submitted are still failing with this version.

[Şadi Çağatay Öztürk]

I am using 0.8.6

[Cary R.]

OK 0.8.6 is the latest 0.8 release so this was fixed in git after the release. Since this is already fixed in git I'm marking this "Works For Me" and closing the report.

[Şadi Çağatay Öztürk]

ok. thanks.