#494 "$fscanf: This task not defined by any modules"

[Anonymous]

When compiling a program to read in test vectors from a file using the $fscanf task, the vvp compiler errors with "$fscanf: This task not defined by any modules. I cannot compile it."

Below is the source code and test bench:

`timescale 1ns / 1ps
`define EOF -1
`define NULL 0
//===================================================================
//
// Simple module to read in test vectors.
// Data is read from the file vectors.txt.
// This file must be formatted <READ|WRITE> <ADDR> <DATA> <COMMENT>
// with spaces between each field
//
//===================================================================

module mcu_model(clk, rst_n, en, addr, data);

parameter FILENAME="vectors.txt";

input clk;
input rst_n;
input en;
output [31:0] addr;
output [31:0] data;

integer fh, r, line;
reg [96*8:1] string;
reg [32*8:1] addr_vec, data_vec;
reg rd_n, wr_n, tristate;

initial begin: file_block
fh=$fopen(FILENAME, "r");
if (fh == `NULL)
disable file_block;
for (line = 1; line <= 5; line=line+1) begin
r = $fgets(string, FILENAME);
if (r == `EOF)
$finish;
@(posedge clk)
if (en) begin
r = $fscanf(FILENAME, " %h %h \n", addr_vec, data_vec);
end
end
end

assign addr = addr_vec;
assign data = (tristate) ? 32'hZZZZ : data_vec;

endmodule

`timescale 1ns / 1ps
//===================================================================
//
// Test bench for the mcu_model.v file.
//
//===================================================================
module mcu_model_tb;

reg en;
reg clk = 1'b0;
reg rst_n;
wire [31:0] addr, data;

time PERIOD = 10; // clock period

mcu_model UUT(
.clk(clk),
.rst_n(rst_n),
.en(en),
.addr(addr),
.data(data) );

always #(PERIOD/2) clk=~clk;

initial begin
$dumpfile("mcu_model.vcd");
$dumpvars(0,mcu_model_tb);

en = 1'b1;
rst_n = 1'b0;
#200;
rst_n = 1'b1;

$finish;
end

endmodule

This is the test vector file, vectors.txt that is read in:

C238 23A7
C24A 1
C23 0
C23 1
FFFF 23

The following is a transcript of the commands used to compile the source code:

Patrick@UNIVAC:~/Desktop/verilog_test/fileio$ iverilog -o mcu_model -s mcu_model_tb mcu_model.v mcu_model_tb.v

Patrick@UNIVAC:~/Desktop/verilog_test/fileio$ vvp mcu_model
$fscanf: This task not defined by any modules. I cannot compile it.
mcu_model: Program not runnable, 1 errors.

OS = Xubuntu 2.6.24-19
Icarus version = 0.8.6 (compiled and installed via source)

[Cary R.]

Logged In: YES
user_id=1651735
Originator: NO

If you are not using the synthesis part of V0.8 (you just need a Verilog simulator), try using the development version (V0.9). It already includes this function. It should not be too hard to back port this to V0.8 if you must use V0.8.

[Cary R.]

Logged In: YES
user_id=1651735
Originator: NO

I have submitted a patch that makes it more obvious that this system function and all the other missing task/functions have not been implemented for V0.8. I will wait a bit longer before closing this report to see if this is really needed in V0.8.

[Cary R.]

Logged In: YES
user_id=1651735
Originator: NO

It has been a week with no reply so I am closing this report. If this is really needed in V0.8 reopen this report or create a new one.