#365 VVP crash due to tristate buffers and child module

[Bionic-Badger]

Snapshot 20070608
Compiled on x86 Linux, GCC version 4.1.2 20060928

When creating an W_DATA-size array of bufif1 tristate buffers, having an output port of size W_DATA, a single enable wire, but using a single wire for the input port sourced from a W_DATA-size port of a module instance, a size assertion causes a core dump:

vvp: vvp_net.cc:2137: vvp_vector8_t resolve(const vvp_vector8_t&, const vvp_vector8_t&): Assertion `a.size() == b.size()' failed.

Changes which prevent the core dump:

- Setting a size > 1 for the net connected to the input port of the bufif1 tristate array. This causes IVerilog to leave ports disconnected and it warns of an array size mismatch.

- Setting the child module's output port size to be 1 will allow it to compile with no errors or warnings.

I've attached a copy of some code that will demonstrate the bug with comments showing various net definitions which prevent the core dump.

[Bionic-Badger]

Example verilog code and comments

[Cary R.]

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This appears to be fixed in the latest development version from git. Or at least it doesn't crash. Here is the message I get:

modules.v:25: warning: Port 1 (oMemWriteData) of child expects 16 bits, got 1.
modules.v:25: : Leaving 15 high bits of the port unconnected.

Please try your base example with a more recent version and let us know the results.