#35 buggy compilation: "UNSUPPORTED LOGIC TYPE: 20"

[depaulfm]

Hi Steve,
v0_8-branch complains about equality operator.
I believe this is a bug? Do you agree?I believe this
is a bug? Do you agree?

In the example below, the equality operator
in the line flagged by '<<<<<----' is parsed by
iverilog with the following result:

UNSUPPORTED LOGIC TYPE: 20

The netlist creates this non-LPM constructs:
"case compare ==="

Example
--------
module ff(rst, clk, q, dl);
input rst;
input clk;
input [4:0] q;
output [4:0] dl;

reg [4:0] d;
wire [4:0] dl;
reg [4:0] state, next_state;

assign dl = d;

always@(posedge clk or posedge rst)
if(rst)
begin
state <= 5'b00000;
end
else
begin
state <= state + 1;//next_state;
end

always@(state or q)
begin
d = state;
case(state)
5'd2: if(q == 5'd2) d = 5'd3; <<<<<<-----
default : d = state;
endcase // case(state)
end
endmodule

Thanks,

[Stephen Williams]

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This is actually a problem with the code generator. It is
complaining about some gates being created by the core
compiler that it does not know how to generate code for.

[Stephen Williams]

Logged In: YES
user_id=97566
Originator: NO

What code generator are you using for this? If the fpga target,
which architecture? The problem here is that there is no code
generator for the EEQ operator. If you tell me what you are
targeting, I'll add it. (Assuming it's a supported target.)

[SourceForge Robot]

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