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#34 error: ...if statement is missing the else clause...
Hi Steve,
I came to this error while trying to generate
LPM for a simple procedural block. It can also
be reproduced by using the PCI core from
OpenCores.org
It seems the Icarus synthesis does not know how
to synthesize a code that is perfectly fine (in
the synthesizable sense).
Since I am using v0.8 I am wondering if you are
planning to support the following construct in the
near future. If not, I just wanted to know if there
was any special reason for not 'accepting' this kind
of construct.
Here's a dummy example:
module ff(rst, clk, q, dl);
input rst;
input clk;
input [4:0] q;
output [4:0] dl;
reg [4:0] d;
wire [4:0] dl;
reg [4:0] state, next_state;
assign dl = d;
always@(posedge clk or posedge rst)
if(rst) begin
state <= 5'b00000;
end
else begin
state <= state + 1;//next_state;
end
always@(state or q)
begin
d = state;
case(state)
5'd2: if(q == 5'd2) d = 5'd3; <<<<------
default : d = state;
endcase // case(state)
end
endmodule
The line with <<<<----- is the one in which Icarus
complain about the missing 'else' statement.
The point is that 'd' is assigned a value before
the 'case statement', which makes this construct
OK for synthesis (does not create a level-latch).
Please, let me know should you need more information.
Thank you,
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This actually seems to be fixed already in the CVS of the
v0_8-branch branch. (Not the main devel trunk.) The thing to
do is to get the current cvs, using the "-r v0_8-branch" tag.
I think I should soon make a v0.8.2 or somesuch, as there
are a lot of synthesis bugs fixed in the v0_8-branch.
Note that v0.8 is a development fork. The main devel trunk
is losing the ability to do synthesis at the same time the
0v.8 branch is gaining new synthesis skills.
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Hi Steve,
Actually, the version I have is the
"verilog-0.8.2.tar.gz". Sorry, I misled you when setting
the 'group' to 'v0.8'.
However, I downloaded it from the Icarus ftp site, not
from the sourceForge.net.
By the way, what is the Iverilog CVS project name?
I tried a few different names buy kept getting "cvs
server: cannot find module `iverilog' - ignored' name
So, if the files in the Icarus ftp are reliable, then this
is still a bug. Do you agree?
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The "group" of v0.8 includes 0.8.2... the entire branch in
fact. The CVS for Icarus Verilog is not on sourceforge, it
is on a private anonymous CVS server at icarus.com. Go to
the home page and follow links from there. There will be
instructions that include the server name and the
recommended exact commands that get you and anonymous cvs.
All the instructions lack is specifics on how to get the
branch. Add "-r v0_8-branch" to the "cvs get" command, like
this:
cvs get -r v0_8-branch -d<cvs-path> verilog
It's in there. The v0.8 branch is actively being worked on,
in spite of the lact of snapshots. I haven't figured out how
to organize snapshot releases.
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v0_8-branch solves the issue. However, it complains
about the equality (in the same flagged line in the
example I provided). I will file another bug report with
more detail.
Thanks Steve,