The Verilog standard specifies that when a $readmemh or
$readmemb task is given both a starting and ending
address, the data file does not contain any embedded
address specifiers, and the number of words in the data
file is less than the range given to the task, a
warning should be issued.
iverilog does not do this.
I have attached a testcase which demonstrates the
situation. I run it as simply:
on Linux, using Icarus Verilog v0.8 from Ubuntu.
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