The Verilog standard specifies that when a $readmemh or
$readmemb task is given both a starting and ending
address, the data file does not contain any embedded
address specifiers, and the number of words in the data
file is less than the range given to the task, a
warning should be issued.
iverilog does not do this.
I have attached a testcase which demonstrates the
situation. I run it as simply:
iverilog bug.v
./a.out
on Linux, using Icarus Verilog v0.8 from Ubuntu.
Testcase showing the described situation, with output from Icarus Verilog and NC Verilog
Patch for devel snapshot 20060409 or v0.8.2
Logged In: YES
user_id=97566
The attached patch adds the missing warning. The patch should apply to the
v0.8 releases or the 20060409 devel snapshot. The path has also been
applied to CVS for both branches.