#235 sorry: trireg nets not supported

[thiede]

verilog-20080418/bin/iverilog test.v
test.v:8: sorry: trireg nets not supported.

module test ( oen, I, C, p);

input oen;
input I;
output C;
inout p;

trireg p;
assign p = oen ? 1'bz : I;
assign C = p;

endmodule

[thiede]

[Nobody/Anonymous]

Logged In: NO

Trireg is a standard/basic verilog feature
It's mandatory when using bi-directional signals.

What it's needed to get it implemented?

[Cary R.]

When we add this functionality do not forget to add trireg to the `default_nettype directive and to consider adding the `default_decay_time and `default_trireg_strength directives.