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#234 Unable to bind wire/reg/memory
verilog-20080418/bin/iverilog test.v
test.v:50: error: Unable to bind wire/reg/memory `i_WEN' in `test.x_it'
test.v:50: error: Unable to elaborate condition expression.
test.v:49: Unable to elaborate statement in task test.x_it at test.v:47.
2 error(s) during elaboration.
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As a workaround; if you explicitly declare i_WEN (wire) at the top level this will compile.
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Here's a more succinct example of the concern. Icarus manages to infer wire declarations in some cases, but not others. Of course, it's terrible form to depend on such implicit behavior in production code, so any `fix' to this needs checking that -Wall will still bark.
module main();
wire bar;
reg rbar;
assign bar=foo1; // no complaints unless -Wall
initial rbar=foo2; // error: Unable to bind wire/reg/memory `foo2' in `main'
endmodule
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Here's a more succinct example of the concern. Icarus manages to infer wire declarations in some cases, but not others. Of course, it's terrible form to depend on such implicit behavior in production code, so any `fix' to this needs checking that -Wall will still bark.
module main();
wire bar;
reg rbar;
assign bar=foo1; // no complaints unless -Wall
initial rbar=foo2; // error: Unable to bind wire/reg/memory `foo2' in `main'
endmodule
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I'm fully aware of the workaround, but since this code went thru several "other" verilog readers without errors (some warnings) I would like iverilog to be able to read it too ...
And yes, it's production code (from a memory vendor) and no, I don't think that using implicit one bit wires is a terrible thing to do.
Stefan
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Git as of Jan 16, this used to elaborate before.
If you uncomment the wire statement everything is fine.
iverilog test1.v
test1.v:3: error: Unable to bind wire/reg/memory `r' in `test'
test1.v:3: internal error: Port expression too complicated for elaboration.
1 error(s) during elaboration.
module test();
// wire r;
a ua ( .r ( !r ));
endmodule
module a ( r );
input r;
endmodule
File Added: test1.v
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Updated priority to math new guidelines
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The test.v example now compiles properly, the test1.v does not quiet yet.
Note that ldoolitt2's example is not correct. The foo2 variable is an r-value, and in behavioral code. These are both contexts that do *not* cause implicit declaration.
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The test1.v example compiles with git as of 23 March 2008. The test1.v example passes an implicitly declared wire within an expression to an input port. I can't see that this is illegal, even though this is increasingly funky coding style.