#198 empty default in case causes internal error

[thiede]

verilog-20070403/bin/iverilog test.v
ivl: net_nex_output.cc:80: virtual void NetCase::nex_output(NexusSet&): Assertion `items_[idx].statement' failed.

If you comment out the "default:;" line it compiles.

module test ();

reg[7:0] a;
reg b;

always @*
begin
b = 1'b0;
case (a)
8'd66: b = 1'b1;
default: ;
endcase
end
endmodule

[thiede]

[Stephen Williams]

Logged In: YES
user_id=97566
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The attached patch fixes the problem and should apply to the 20070227 snapshot. It is also available from CVS as of 5 April 2007, or from the next snapshot.

I've also added pr1694427.v to the ivtest regression test suite.

File Added: pr1694427.patch

[Stephen Williams]

Patch for devel snapshot 20070227

[Uwe Bonnes]

A similar error still happens with git iverilog of 2008 oct 14 with an empty "default : ;" in a generate clause. The Xilinx ISE verilog language template used BRAM_SDP_MACRO.v to help infer dual port rams. This file used "default : ;", and I hope i boiled down the problem in appended verilog file.
module test();
parameter NAME = "test";
wire i=0;

generate
case(NAME)
"test" :
begin : t
assign i = 1;
end
default : ;
endcase // case (NAME)
endgenerate

initial
begin
$display("i %d", i);
#1 $finish;
end

endmodule // test

[Cary R.]

I have submitted a patch that fixes this for all generate case items. The parser was using the wrong item type (missing the optional ";") construct.