This program fails (v 0.8.3, "iverilog test.v, ./a.out"):
module test;
initial
main;
task main;
integer foo;
begin
foo = 0;
while(foo < 5) begin: inner
foo = foo + 1;
end
$write("expected %d; got %d\n", 5, foo);
end
endtask
endmodule
The output is "expected 5; got x".
The program works correctly if the block identifier (":inner") is removed.
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Added pr1645277.v to the ivtest regression test suite. The current devel CVS (as of 2 Feb 2007)
executes this test correctly, but the v0.8 branch needs to be looked at. So the report can
remain open.
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Here is a back ported patch from development that fixes the problem.
File Added: 0001-v0_8-clear-expression-look-aside-for-transient-thre.patch
Patch file