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#1008 Target code contains a syntax error

devel
closed-fixed
nobody
None
6
2016-11-25
2016-08-24
Stacey Cambpell
No

Attached Verilog source compiles cleanly, however target code contains a syntax error.

$ iverilog -Wall -o test test.v
$ ./test
./test:90: syntax error

I am building iverilog on Linux and Cygwin/Windows from the git master branch.

$ cd iverilog
$ git status .
On branch master
Your branch is up-to-date with 'origin/master'.
$ date
Wed Aug 24 11:54:37 PDT 2016

1 Attachments
test.v

Related

Bugs: #1008

Discussion

  • Martin Whitaker

    Martin Whitaker - 2016-08-30
    • Priority: 5 --> 6
     

    • Stephen Williams

      Stephen Williams - 2016-08-30

      I'll take a look.

      On 08/30/2016 03:23 PM, Martin Whitaker wrote:

      • Priority: 5 --> 6
      • Comment:

      I've spent some time investigating this, but need some input from Steve
      to know how to proceed. The bug can be reproduced by this simple test case:

      module test();

      wire [3:0] a = 4'd0;

      wire signed [3:0] b[1:0];

      assign b[0] = $signed(a);

      endmodule

      This fails because the tgt-vvp code generator outputs |.alias/s|
      statements, which vvp doesn't recognise. However, fixing this (either by
      changing tgt-vvp to output |.alias| statements or by changing vvp to
      recognise |.alias/s| statements) doesn't get us much further, resulting
      in a vvp assertion failure:

      vvp: ../../source/vvp/array.cc:806: void __vpiArray::alias_word(long unsigned int, vpiHandle, int, int): Assertion `msb.get_value() == msb_' failed.

      The same assertion failure can be seen by changing the test case to:

      module test();

      wire [3:0] a = 4'd0;

      wire [3:0] b[1:0];

      assign b[0] = $unsigned(a);

      endmodule

      Removing the assert statement in |__vpiArray::alias_word| allows the
      test case to run, but if we then add the statement:

      initial $display(b[0]);

      to the test case, we get another vvp error:

      unresolved vpi name lookup: v0x1d800c0_0

      The bug does not occur if the continuous assignment is changed to:

      assign b[0] = a;

      because then the compiler inserts a BUFZ between |a| and |b[0]|.

      So my questions for Steve are:
      1) Is it valid for the compiler to connect |a| and |b[0]| to a single
      nexus, and hence cause tgt-vvp to output |.alias| statements?
      2) If so, why is it inserting a BUFZ for the |b[0] = a| case?
      3) If not, what circumstances should cause |.alias| statements to be
      generated? They appear to be broken, but none of the tests in the test
      suite exercise this.

      [bugs:#1008] https://sourceforge.net/p/iverilog/bugs/1008/ Target
      code contains a syntax error

      Status: open
      Group: devel
      Created: Wed Aug 24, 2016 06:56 PM UTC by Stacey Cambpell
      Last Updated: Wed Aug 24, 2016 06:56 PM UTC
      Owner: nobody
      Attachments:

      Attached Verilog source compiles cleanly, however target code contains a
      syntax error.

      $ iverilog -Wall -o test test.v
      $ ./test
      ./test:90: syntax error

      I am building iverilog on Linux and Cygwin/Windows from the git master
      branch.

      $ cd iverilog
      $ git status .
      On branch master
      Your branch is up-to-date with 'origin/master'.
      $ date
      Wed Aug 24 11:54:37 PDT 2016

      Sent from sourceforge.net because you indicated interest in
      https://sourceforge.net/p/iverilog/bugs/1008/

      To unsubscribe from further messages, please visit
      https://sourceforge.net/auth/subscriptions/

      --
      Steve Williams "The woods are lovely, dark and deep.
      steve at icarus.com But I have promises to keep,
      http://www.icarus.com and lines to code before I sleep,
      http://www.picturel.com And lines to code before I sleep."

       

      Related

      Bugs: #1008

      • Stephen Williams

        Stephen Williams - 2016-08-31

        I think the right answer is that the vvp target should generate
        the .alias instead of .alias/s record. The question I'm trying to
        answer is why that assertion failed. It looks like some details
        for the "b" array are not being filled in properly, so the cross-
        check when binding the alias to the array word is failing.

        On 08/30/2016 03:54 PM, Stephen Williams wrote:

        I'll take a look.

        On 08/30/2016 03:23 PM, Martin Whitaker wrote:

          * /Priority/: 5 --> 6
  * /Comment/:

I've spent some time investigating this, but need some input from Steve
to know how to proceed. The bug can be reproduced by this simple
test case:

module test();

wire [3:0] a = 4'd0;

wire signed [3:0] b[1:0];

assign b[0] = $signed(a);

endmodule

This fails because the tgt-vvp code generator outputs |.alias/s|
statements, which vvp doesn't recognise. However, fixing this (either by
changing tgt-vvp to output |.alias| statements or by changing vvp to
recognise |.alias/s| statements) doesn't get us much further, resulting
in a vvp assertion failure:

vvp: ../../source/vvp/array.cc:806: void __vpiArray::alias_word(long
unsigned int, vpiHandle, int, int): Assertion `msb.get_value() ==
msb_' failed.

The same assertion failure can be seen by changing the test case to:

module test();

wire [3:0] a = 4'd0;

wire [3:0] b[1:0];

assign b[0] = $unsigned(a);

endmodule

Removing the assert statement in |__vpiArray::alias_word| allows the
test case to run, but if we then add the statement:

initial $display(b[0]);

to the test case, we get another vvp error:

unresolved vpi name lookup: v0x1d800c0_0

The bug does not occur if the continuous assignment is changed to:

assign b[0] = a;

because then the compiler inserts a BUFZ between |a| and |b[0]|.

So my questions for Steve are:
1) Is it valid for the compiler to connect |a| and |b[0]| to a single
nexus, and hence cause tgt-vvp to output |.alias| statements?
2) If so, why is it inserting a BUFZ for the |b[0] = a| case?
3) If not, what circumstances should cause |.alias| statements to be
generated? They appear to be broken, but none of the tests in the test
suite exercise this.

------------------------------------------------------------------------

/[bugs:#1008] <https://sourceforge.net/p/iverilog/bugs/1008/>
https://sourceforge.net/p/iverilog/bugs/1008/ Target
code contains a syntax error/

/Status:/ open
/Group:/ devel
/Created:/ Wed Aug 24, 2016 06:56 PM UTC by Stacey Cambpell
/Last Updated:/ Wed Aug 24, 2016 06:56 PM UTC
/Owner:/ nobody
/Attachments:/

  * test.v
    https://sourceforge.net/p/iverilog/bugs/1008/attachment/test.v
    (4.3 kB; application/octet-stream)

Attached Verilog source compiles cleanly, however target code contains a
syntax error.

$ iverilog -Wall -o test test.v
$ ./test
./test:90: syntax error

I am building iverilog on Linux and Cygwin/Windows from the git master
branch.

$ cd iverilog
$ git status .
On branch master
Your branch is up-to-date with 'origin/master'.
$ date
Wed Aug 24 11:54:37 PDT 2016

------------------------------------------------------------------------

Sent from sourceforge.net because you indicated interest in
https://sourceforge.net/p/iverilog/bugs/1008/

To unsubscribe from further messages, please visit
https://sourceforge.net/auth/subscriptions/

        --
        Steve Williams "The woods are lovely, dark and deep.
        steve at icarus.com But I have promises to keep,
        http://www.icarus.com and lines to code before I sleep,
        http://www.picturel.com And lines to code before I sleep."

        [bugs:#1008] https://sourceforge.net/p/iverilog/bugs/1008/ Target
        code contains a syntax error

        Status: open
        Group: devel
        Created: Wed Aug 24, 2016 06:56 PM UTC by Stacey Cambpell
        Last Updated: Tue Aug 30, 2016 10:23 PM UTC
        Owner: nobody
        Attachments:

        Attached Verilog source compiles cleanly, however target code contains a
        syntax error.

        $ iverilog -Wall -o test test.v
        $ ./test
        ./test:90: syntax error

        I am building iverilog on Linux and Cygwin/Windows from the git master
        branch.

        $ cd iverilog
        $ git status .
        On branch master
        Your branch is up-to-date with 'origin/master'.
        $ date
        Wed Aug 24 11:54:37 PDT 2016

        Sent from sourceforge.net because you indicated interest in
        https://sourceforge.net/p/iverilog/bugs/1008/

        To unsubscribe from further messages, please visit
        https://sourceforge.net/auth/subscriptions/

        --
        Steve Williams "The woods are lovely, dark and deep.
        steve at icarus.com But I have promises to keep,
        http://www.icarus.com and lines to code before I sleep,
        http://www.picturel.com And lines to code before I sleep."

         

        Related

        Bugs: #1008

        • Martin Whitaker

          Martin Whitaker - 2016-08-31

          On 31/08/16 17:36, Stephen Williams wrote:

          I think the right answer is that the vvp target should generate
          the .alias instead of .alias/s record. The question I'm trying to
          answer is why that assertion failed. It looks like some details
          for the "b" array are not being filled in properly, so the cross-
          check when binding the alias to the array word is failing.

          Then I think the fix is to replace the .alias with a .net. I've just found this:

          commit 8247d3ef458fcdc33c5738fc3d613fc2c696ef4e
          Author: Stephen Williams steve@icarus.com
          Date: Wed Oct 14 21:40:15 2009 -0700

           The .alias for nets is no longer useful.

 In the olden days, the .alias was necessary to create a net name
 that is an alias to an existing net in the netlist. But now that
 the .net no longer creates a node in the netlist, ALL .net objects
 are aliases of a sort, so this (mis)feature gets in the way.

          My only concern is that collapsing the nets will cause trouble in other targets (e.g. the vlog95
          target).

           

          • Stephen Williams

            Stephen Williams - 2016-08-31

            Good find! Gosh, that's 6 years ago. We should probably look for
            all the places where the net form of the .alias are generate in
            the tgt-vvp. I also will have to re-learn now a net would be
            bound up to a word. It might be that we re-use the .alias syntax
            in this case to find the target node in the netlist.

            On 08/31/2016 10:44 AM, Martin Whitaker wrote:

            On 31/08/16 17:36, Stephen Williams wrote:

            I think the right answer is that the vvp target should generate
the .alias instead of .alias/s record. The question I'm trying to
answer is why that assertion failed. It looks like some details
for the "b" array are not being filled in properly, so the cross-
check when binding the alias to the array word is failing.

            Then I think the fix is to replace the |.alias| with a |.net|. I've just
            found this:

            commit 8247d3ef458fcdc33c5738fc3d613fc2c696ef4e
            Author: Stephen Williams steve@icarus.com steve@icarus.com
            Date: Wed Oct 14 21:40:15 2009 -0700

            The .alias for nets is no longer useful.

            In the olden days, the .alias was necessary to create a net name
            that is an alias to an existing net in the netlist. But now that
            the .net no longer creates a node in the netlist, ALL .net objects
            are aliases of a sort, so this (mis)feature gets in the way.

            My only concern is that collapsing the nets will cause trouble in other
            targets (e.g. the vlog95
            target).

            [bugs:#1008] https://sourceforge.net/p/iverilog/bugs/1008/ Target
            code contains a syntax error

            Status: open
            Group: devel
            Created: Wed Aug 24, 2016 06:56 PM UTC by Stacey Cambpell
            Last Updated: Tue Aug 30, 2016 10:23 PM UTC
            Owner: nobody
            Attachments:

            Attached Verilog source compiles cleanly, however target code contains a
            syntax error.

            $ iverilog -Wall -o test test.v
            $ ./test
            ./test:90: syntax error

            I am building iverilog on Linux and Cygwin/Windows from the git master
            branch.

            $ cd iverilog
            $ git status .
            On branch master
            Your branch is up-to-date with 'origin/master'.
            $ date
            Wed Aug 24 11:54:37 PDT 2016

            Sent from sourceforge.net because you indicated interest in
            https://sourceforge.net/p/iverilog/bugs/1008/

            To unsubscribe from further messages, please visit
            https://sourceforge.net/auth/subscriptions/

            --
            Steve Williams "The woods are lovely, dark and deep.
            steve at icarus.com But I have promises to keep,
            http://www.icarus.com and lines to code before I sleep,
            http://www.picturel.com And lines to code before I sleep."

             

            Related

            Bugs: #1008

            • Stephen Williams

              Stephen Williams - 2016-08-31

              I've looked at this some, and I think the right answer is to
              generate a .net/s record here instead of the .alias/s record.
              This is consistent with how the other words of the net array
              are handled.

              Now to figure out how to make that happen...

              On 08/31/2016 10:51 AM, Stephen Williams wrote:

              Good find! Gosh, that's 6 years ago. We should probably look for
              all the places where the net form of the .alias are generate in
              the tgt-vvp. I also will have to re-learn now a net would be
              bound up to a word. It might be that we re-use the .alias syntax
              in this case to find the target node in the netlist.

              On 08/31/2016 10:44 AM, Martin Whitaker wrote:

              On 31/08/16 17:36, Stephen Williams wrote:

I think the right answer is that the vvp target should generate
the .alias instead of .alias/s record. The question I'm trying to
answer is why that assertion failed. It looks like some details
for the "b" array are not being filled in properly, so the cross-
check when binding the alias to the array word is failing.

Then I think the fix is to replace the |.alias| with a |.net|. I've just
found this:

commit 8247d3ef458fcdc33c5738fc3d613fc2c696ef4e
Author: Stephen Williams steve@icarus.com steve@icarus.com
<mailto:steve@icarus.com>
Date: Wed Oct 14 21:40:15 2009 -0700

The .alias for nets is no longer useful.

In the olden days, the .alias was necessary to create a net name
that is an alias to an existing net in the netlist. But now that
the .net no longer creates a node in the netlist, ALL .net objects
are aliases of a sort, so this (mis)feature gets in the way.

My only concern is that collapsing the nets will cause trouble in other
targets (e.g. the vlog95
target).

------------------------------------------------------------------------

/[bugs:#1008] <https://sourceforge.net/p/iverilog/bugs/1008/>
https://sourceforge.net/p/iverilog/bugs/1008/ Target
code contains a syntax error/

/Status:/ open
/Group:/ devel
/Created:/ Wed Aug 24, 2016 06:56 PM UTC by Stacey Cambpell
/Last Updated:/ Tue Aug 30, 2016 10:23 PM UTC
/Owner:/ nobody
/Attachments:/

  * test.v
    https://sourceforge.net/p/iverilog/bugs/1008/attachment/test.v
    (4.3 kB; application/octet-stream)

Attached Verilog source compiles cleanly, however target code contains a
syntax error.

$ iverilog -Wall -o test test.v
$ ./test
./test:90: syntax error

I am building iverilog on Linux and Cygwin/Windows from the git master
branch.

$ cd iverilog
$ git status .
On branch master
Your branch is up-to-date with 'origin/master'.
$ date
Wed Aug 24 11:54:37 PDT 2016

------------------------------------------------------------------------

Sent from sourceforge.net because you indicated interest in
https://sourceforge.net/p/iverilog/bugs/1008/

To unsubscribe from further messages, please visit
https://sourceforge.net/auth/subscriptions/

              --
              Steve Williams "The woods are lovely, dark and deep.
              steve at icarus.com But I have promises to keep,
              http://www.icarus.com and lines to code before I sleep,
              http://www.picturel.com And lines to code before I sleep."

              [bugs:#1008] https://sourceforge.net/p/iverilog/bugs/1008/ Target
              code contains a syntax error

              Status: open
              Group: devel
              Created: Wed Aug 24, 2016 06:56 PM UTC by Stacey Cambpell
              Last Updated: Tue Aug 30, 2016 10:23 PM UTC
              Owner: nobody
              Attachments:

              Attached Verilog source compiles cleanly, however target code contains a
              syntax error.

              $ iverilog -Wall -o test test.v
              $ ./test
              ./test:90: syntax error

              I am building iverilog on Linux and Cygwin/Windows from the git master
              branch.

              $ cd iverilog
              $ git status .
              On branch master
              Your branch is up-to-date with 'origin/master'.
              $ date
              Wed Aug 24 11:54:37 PDT 2016

              Sent from sourceforge.net because you indicated interest in
              https://sourceforge.net/p/iverilog/bugs/1008/

              To unsubscribe from further messages, please visit
              https://sourceforge.net/auth/subscriptions/

              --
              Steve Williams "The woods are lovely, dark and deep.
              steve at icarus.com But I have promises to keep,
              http://www.icarus.com and lines to code before I sleep,
              http://www.picturel.com And lines to code before I sleep."

               

              Related

              Bugs: #1008

              • Stephen Williams

                Stephen Williams - 2016-08-31

                I've pushed a possible fix. It seems to at least fix this case,
                and the test suite seems to run OK. I've also pushed a test into
                the ivtest suite.

                On 08/31/2016 01:11 PM, Stephen Williams wrote:

                I've looked at this some, and I think the right answer is to
                generate a .net/s record here instead of the .alias/s record.
                This is consistent with how the other words of the net array
                are handled.

                Now to figure out how to make that happen...

                On 08/31/2016 10:51 AM, Stephen Williams wrote:

                Good find! Gosh, that's 6 years ago. We should probably look for
all the places where the net form of the .alias are generate in
the tgt-vvp. I also will have to re-learn now a net would be
bound up to a word. It might be that we re-use the .alias syntax
in this case to find the target node in the netlist.

On 08/31/2016 10:44 AM, Martin Whitaker wrote:

On 31/08/16 17:36, Stephen Williams wrote:

I think the right answer is that the vvp target should generate
the .alias instead of .alias/s record. The question I'm trying to
answer is why that assertion failed. It looks like some details
for the "b" array are not being filled in properly, so the cross-
check when binding the alias to the array word is failing.

Then I think the fix is to replace the |.alias| with a |.net|. I've just
found this:

commit 8247d3ef458fcdc33c5738fc3d613fc2c696ef4e
Author: Stephen Williams steve@icarus.com steve@icarus.com
<mailto:steve@icarus.com>
Date: Wed Oct 14 21:40:15 2009 -0700

The .alias for nets is no longer useful.

In the olden days, the .alias was necessary to create a net name
that is an alias to an existing net in the netlist. But now that
the .net no longer creates a node in the netlist, ALL .net objects
are aliases of a sort, so this (mis)feature gets in the way.

My only concern is that collapsing the nets will cause trouble in other
targets (e.g. the vlog95
target).

------------------------------------------------------------------------

/[bugs:#1008] <https://sourceforge.net/p/iverilog/bugs/1008/>
https://sourceforge.net/p/iverilog/bugs/1008/ Target
code contains a syntax error/

/Status:/ open
/Group:/ devel
/Created:/ Wed Aug 24, 2016 06:56 PM UTC by Stacey Cambpell
/Last Updated:/ Tue Aug 30, 2016 10:23 PM UTC
/Owner:/ nobody
/Attachments:/

  * test.v
    https://sourceforge.net/p/iverilog/bugs/1008/attachment/test.v
    (4.3 kB; application/octet-stream)

Attached Verilog source compiles cleanly, however target code contains a
syntax error.

$ iverilog -Wall -o test test.v
$ ./test
./test:90: syntax error

I am building iverilog on Linux and Cygwin/Windows from the git master
branch.

$ cd iverilog
$ git status .
On branch master
Your branch is up-to-date with 'origin/master'.
$ date
Wed Aug 24 11:54:37 PDT 2016

------------------------------------------------------------------------

Sent from sourceforge.net because you indicated interest in
https://sourceforge.net/p/iverilog/bugs/1008/

To unsubscribe from further messages, please visit
https://sourceforge.net/auth/subscriptions/

-- 
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."

------------------------------------------------------------------------

/[bugs:#1008] <https://sourceforge.net/p/iverilog/bugs/1008/>
https://sourceforge.net/p/iverilog/bugs/1008/ Target
code contains a syntax error/

/Status:/ open
/Group:/ devel
/Created:/ Wed Aug 24, 2016 06:56 PM UTC by Stacey Cambpell
/Last Updated:/ Tue Aug 30, 2016 10:23 PM UTC
/Owner:/ nobody
/Attachments:/

  * test.v
    https://sourceforge.net/p/iverilog/bugs/1008/attachment/test.v
    (4.3 kB; application/octet-stream)

Attached Verilog source compiles cleanly, however target code contains a
syntax error.

$ iverilog -Wall -o test test.v
$ ./test
./test:90: syntax error

I am building iverilog on Linux and Cygwin/Windows from the git master
branch.

$ cd iverilog
$ git status .
On branch master
Your branch is up-to-date with 'origin/master'.
$ date
Wed Aug 24 11:54:37 PDT 2016

------------------------------------------------------------------------

Sent from sourceforge.net because you indicated interest in
https://sourceforge.net/p/iverilog/bugs/1008/

To unsubscribe from further messages, please visit
https://sourceforge.net/auth/subscriptions/

                --
                Steve Williams "The woods are lovely, dark and deep.
                steve at icarus.com But I have promises to keep,
                http://www.icarus.com and lines to code before I sleep,
                http://www.picturel.com And lines to code before I sleep."

                [bugs:#1008] https://sourceforge.net/p/iverilog/bugs/1008/ Target
                code contains a syntax error

                Status: open
                Group: devel
                Created: Wed Aug 24, 2016 06:56 PM UTC by Stacey Cambpell
                Last Updated: Tue Aug 30, 2016 10:23 PM UTC
                Owner: nobody
                Attachments:

                Attached Verilog source compiles cleanly, however target code contains a
                syntax error.

                $ iverilog -Wall -o test test.v
                $ ./test
                ./test:90: syntax error

                I am building iverilog on Linux and Cygwin/Windows from the git master
                branch.

                $ cd iverilog
                $ git status .
                On branch master
                Your branch is up-to-date with 'origin/master'.
                $ date
                Wed Aug 24 11:54:37 PDT 2016

                Sent from sourceforge.net because you indicated interest in
                https://sourceforge.net/p/iverilog/bugs/1008/

                To unsubscribe from further messages, please visit
                https://sourceforge.net/auth/subscriptions/

                --
                Steve Williams "The woods are lovely, dark and deep.
                steve at icarus.com But I have promises to keep,
                http://www.icarus.com and lines to code before I sleep,
                http://www.picturel.com And lines to code before I sleep."

                 

                Related

                Bugs: #1008

  • Martin Whitaker

    Martin Whitaker - 2016-08-30

    I've spent some time investigating this, but need some input from Steve to know how to proceed. The bug can be reproduced by this simple test case:

    module test();

wire [3:0] a = 4'd0;       

wire signed [3:0] b[1:0];

assign b[0] = $signed(a);

endmodule

    This fails because the tgt-vvp code generator outputs .alias/s statements, which vvp doesn't recognise. However, fixing this (either by changing tgt-vvp to output .alias statements or by changing vvp to recognise .alias/s statements) doesn't get us much further, resulting in a vvp assertion failure:

    vvp: ../../source/vvp/array.cc:806: void __vpiArray::alias_word(long unsigned int, vpiHandle, int, int): Assertion `msb.get_value() == msb_' failed.

    The same assertion failure can be seen by changing the test case to:

    module test();

wire [3:0] a = 4'd0;       

wire [3:0] b[1:0];

assign b[0] = $unsigned(a);

endmodule

    Removing the assert statement in __vpiArray::alias_word allows the test case to run, but if we then add the statement:

    initial $display(b[0]);

    to the test case, we get another vvp error:

    unresolved vpi name lookup: v0x1d800c0_0

    The bug does not occur if the continuous assignment is changed to:

    assign b[0] = a;

    because then the compiler inserts a BUFZ between a and b[0].

    So my questions for Steve are:
    1) Is it valid for the compiler to connect a and b[0] to a single nexus, and hence cause tgt-vvp to output .alias statements?
    2) If so, why is it inserting a BUFZ for the b[0] = a case?
    3) If not, what circumstances should cause .alias statements to be generated? They appear to be broken, but none of the tests in the test suite exercise this.

     

  • Martin Whitaker

    Martin Whitaker - 2016-11-25
    • status: open --> closed-fixed
     

  • Martin Whitaker

    Martin Whitaker - 2016-11-25

    I believe this one was fixed a while ago, but the ticket didn't get closed.

     

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