Fast Tabular Local Logic Minimizer download

Given a circuit described in terms of common CMOS logic gates, this is capable of minimizing logic area by repetitive examination of sets of three gates, utilizing a pre-computed lookup table of pre-optimized replacements. Reductions include XOR gates and can be extended to 3-input logic gates.

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License

GNU Library or Lesser General Public License version 3.0 (LGPLv3)

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Additional Project Details

Intended Audience

Engineering

Programming Language

C++

Related Categories

C++ Electronic Design Automation (EDA) Software

Registered

2014-09-16

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