[Edumips64-commit] SF.net SVN: edumips64:[613] paper/ieee-tedu

[<sv...@ed...>]

Revision: 613
          https://www.edumips.org/changeset/613
Author:   lupino3
Date:     2011-06-03 14:48:42 +0200 (Fri, 03 Jun 2011)
Log Message:
-----------
Fixed 1k typo

Modified Paths:
--------------
    paper/ieee-tedu/conclusions.tex
    paper/ieee-tedu/paper.tex
    paper/ieee-tedu/related-works.tex
    paper/ieee-tedu/survey.tex
    paper/ieee-tedu/teaching.tex

Modified: paper/ieee-tedu/conclusions.tex
===================================================================
--- paper/ieee-tedu/conclusions.tex	2011-06-03 11:19:00 UTC (rev 612)
+++ paper/ieee-tedu/conclusions.tex	2011-06-03 12:48:42 UTC (rev 613)
@@ -13,4 +13,4 @@
 We evaluated the impact of the adoption of the simulator on the teaching
 process by means of a survey compiled by students after the completion of the
 course; thanks to this feedback, we found that \EM{} is perceived as a good
-educational aid, and spotted its strengths and weaknessess.
+educational aid, and spotted its strengths and weaknesses.

Modified: paper/ieee-tedu/paper.tex
===================================================================
--- paper/ieee-tedu/paper.tex	2011-06-03 11:19:00 UTC (rev 612)
+++ paper/ieee-tedu/paper.tex	2011-06-03 12:48:42 UTC (rev 613)
@@ -67,9 +67,9 @@
 \title{Supporting Undergraduate Computer Architecture Students using a Visual
 MIPS64 CPU Simulator}
 
-\author{Andrea Spadaccini, \emph{Student Member, IEEE}, Davide Patti,
-\emph{Member, IEEE}, Maurizio Palesi, \emph{Member, IEEE}
-and Fabrizio Fazzino, \emph{Member, IEEE}\thanks{A. Spadaccini and D. Patti are with the Dipartimento di
+\author{Davide~Patti,~\emph{Member,~IEEE}, Andrea~Spadaccini,~\emph{Graduate~Student~Member,~IEEE}, 
+Maurizio~Palesi,~\emph{Member,~IEEE}, Fabrizio~Fazzino,~\emph{Member,~IEEE}
+and Vincenzo~Catania\thanks{D. Patti, A. Spadaccini and V. Catania are with the Dipartimento di
     Ingegneria Elettrica, Elettronica ed Informatica, University of
     Catania, Catania, Italy (email:
     \{andrea.spadaccini,davide.patti\}@dieei.unict.it).

Modified: paper/ieee-tedu/related-works.tex
===================================================================
--- paper/ieee-tedu/related-works.tex	2011-06-03 11:19:00 UTC (rev 612)
+++ paper/ieee-tedu/related-works.tex	2011-06-03 12:48:42 UTC (rev 613)
@@ -1,10 +1,10 @@
 \section{Related Works}
 \label{sec:related-works}
 
-Several different tools and methologies have been adopted
+Several different tools and methodologies have been adopted
 in order to enhance the learning process of the basic concepts of
 CPU organization usually taught in introductory Computer Architecture courses.
-Some approaches focuse on the adopted framework (e.g.
+Some approaches focus on the adopted framework (e.g.
 simulators, web-based learning, games), while others try to exploit the positive
 effect of collaborative projects in improving students' motivation.
 
@@ -15,11 +15,11 @@
 produced.  
 An educational experience of teaching computer architecture topics
 using a project-based learning is described and evaluated
-in~\cite{Martinez-Mones2005}. The main idea is using a collaborative approch
+in~\cite{Martinez-Mones2005}. The main idea is using a collaborative approach
 where students are assigned to different subprojects but still have to
 exchange some acquired knowledge in order to complete their tasks.
 Authors of~\cite{Verginis2011} present a web-based environment to
-support the learning process in  introductory conputer science course
+support the learning process in  introductory computer science course
 using a customizable e-learning approach.
 
 %tool oriented
@@ -36,5 +36,5 @@
 Computer Architecture and Engineering  to teach some topics related to
 the tuning of cache parameters with the aim of optimizing performance and energy
 consumption.  In~\cite{Sahuquillo2007} authors present a pedagogical
-tool for dealing with code-based exercises expressely focused on cache
+tool for dealing with code-based exercises expressly focused on cache
 memory related topics.

Modified: paper/ieee-tedu/survey.tex
===================================================================
--- paper/ieee-tedu/survey.tex	2011-06-03 11:19:00 UTC (rev 612)
+++ paper/ieee-tedu/survey.tex	2011-06-03 12:48:42 UTC (rev 613)
@@ -31,11 +31,11 @@
 Summarizing these results, it can definitely be assumed that the choice of using Java
 as a cross-platform technology did not penalize the user-experience from
 both the performance and visual points of view, since only a
-neglegible fraction of the users rated \EM{} as less than sufficient.
+negligible fraction of the users rated \EM{} as less than sufficient.
 
 \subsection{Impact on Learning}
 The percent of the time spent by the students on \EM{} is an indicator
-of the role played by the laboratory-based methology in the course. Only a small percentage of
+of the role played by the laboratory-based methodology in the course. Only a small percentage of
 them, less than $8\%$, used \EM{} for less than 10\% of the time
 period ranging from the beginning of the course to the exam. About
 $20\%$ of them used \EM{} for the $20\%-30\%$ of the time, whereas the
@@ -50,7 +50,8 @@
 \end{figure}
 An interesting issue to investigate was the impact of the adopted
 methodology  on the understanding of the different topics encountered during the
-course. Note that some topics that are usually strictly related to the theoric
+course. Note that some topics that are usually strictly related to the
+theoretical
 part of a computer architecture course were deliberately included, in order to
 capture more accurately to which extent, even indirectly, the
 adoption of \EM{} can affect the learning process and the students'
@@ -59,6 +60,6 @@
 different power) all the topics presented in our survey: it can
 be observed an obvious predominance of topics like 
 registers and data encoding - due to bit-accurate encoding 
-- and the assembly programming and pipelining, positevely
+- and the assembly programming and pipelining, positively
 impacted by the visual representation of the CPU during the execution of
 instructions flow.

Modified: paper/ieee-tedu/teaching.tex
===================================================================
--- paper/ieee-tedu/teaching.tex	2011-06-03 11:19:00 UTC (rev 612)
+++ paper/ieee-tedu/teaching.tex	2011-06-03 12:48:42 UTC (rev 613)
@@ -32,7 +32,7 @@
 will not only require the teacher to explain the fundamental concepts of
 instruction-set architectures and assembly language, but also hexadecimal number conversions,
 instruction encoding (with the three main types: R-type, I-type and J-type)
-and even the concept of endianess (ordering of byte in words into memory).
+and even the concept of endianness (ordering of byte in words into memory).
 
 So, a first step with \EM{} should be to show how an assembly source
 file written following a MIPS-like syntax is loaded into memory and
@@ -57,7 +57,7 @@
 \item \emph{Maximize the memory encoding window and highlight some lines, then
 try to find the corresponding snippet of code in the text editor.}
 \item \emph{Choose one of the lines in the memory or code window of \EM{}
-and try to explain the meaning of the exadecimal value associated to
+and try to explain the meaning of the hexadecimal value associated to
 them.}
 \end{itemize}
 
@@ -152,7 +152,7 @@
 \EM{}. There are two main classes of assignments that involve the usage of the
 \texttt{SYSCALL} instruction: 
 \begin{itemize}
-\item Assigments that test the students' ability to put properly the inputs
+\item Assignments that test the students' ability to put properly the inputs
 of the \texttt{SYSCALL} in the \texttt{.data} section and then get the outputs when
 the \texttt{SYSCALL} has ended 
 \item Assignments that stress the usage of \texttt{SYSCALL}
@@ -201,7 +201,7 @@
 total time affected by the enhancement and $S_{e}$ the speedup of the improved
 part of the system.
 
-Using \EM{} in conjuction with DineroIV,
+Using \EM{} in conjunction with DineroIV,
 simple assignments can be designed in order to help students to
 understand how the overall performance of the system is governed by
 the slowest component.
@@ -210,9 +210,9 @@
 \begin{itemize}
 \item Assignments that ask them to compute which will be the
 speedup of the system if a particular component improves its
-perfomances, in other words, the direct usage of Amdahl's law in order
+performances, in other words, the direct usage of Amdahl's law in order
 to compute $S_{overall}$ from a given $F_e$ and $S_e$. 
-\item Assignments that ask students to find which would be the
+\item Assignments that ask students to find which would be 
 the required $S_e$ of a particular component in order to achieve a
 global overall system speedup. This is an inverse usage of
 Amdahl's law, that is, finding $S_e$ from a given desired
@@ -223,16 +223,16 @@
 \begin{itemize}
 \item \emph{Starting from the results obtained when executing a given MIPS64 program
 code on separated instruction and data caches, compute which overall
-speedup would be achieved if the L1D data cache had only half of the
+speedup would be achieved if the L1 data cache had only half of the
 previously reported demand misses.}
 \item \emph{Starting from the results obtained when executing your program
-code on unified L1 cache memory, find which miss penality would be
+code on unified L1 cache memory, find which miss penalty would be
 needed to get and overall system speedup of $30\%$ in performance.}
 \end{itemize}
 
-Both assigments stress students' ability to compute quantitatively the
+Both assignments stress students' ability to compute quantitatively the
 correct $F_e$ from execution statistics. A very interesting feature is
 present in the second category, which can result in a negative value
 for $S_e$; this is useful to make the students understand that 
-sometimes a desidered speedup cannot be obtained, no matter how big is the
+sometimes a desired speedup cannot be obtained, no matter how big is the
 $S_e$ of the component improved.