Re: [E1000-devel] Symmetric hashing for ixgbe driver?

[Cooper F. N. <cn...@uc...>]

Hi Michal,

I have a config that seems to be working well for us on our EOL hardware
in RSS mode.  Future builds will use your new design.

> #Set 4k PCI reads (needs PCI ID of vendor)
> setpci -v -d 8086:10fb e6.b=2e

> #Set IRQ coalescing timer.
> ethtool -C eth2 rx-usecs 1000
> #Set 4k ring buffer
> ethtool -G eth2 rx 4096
> #Set low entropy symmetric hash key
> ethtool -X eth2 hkey 65:da:65:da:65:da:65:da:65:da:65:da:65:da:65:da:65:da:65:da:65:da:65:da:65:da:65:da:65:da:65:da:65:da:65:da:65:da:65:da

Using large PCI reads, ring-buffers and IRQ coalescing mitigates the
issues you describe somewhat.

-Coop

On 11/16/2016 4:51 PM, Michał Purzyński wrote:
> Yes, that's ATR with OS scheduler reordering frames, I believe.
> There's even a paper about that. It actually has to reorder packets
> now that I think about that.
> 
> Disable ATR, all offloading, set symmetric hashing and pin interrupts
> and IDS workers. Should work - my quick tests with the Bro IDS which
> logs flags as they come, were successful.
> 
> I'm not sure you'll get a lot of performance improvements - with the
> constant switching between the userspace and a kernel space. TLB
> trashing (albeit tagged now), partial cache flush. Worth testing.
> 
> One thing we'd like to ask Intel for is the ability to set symmetric
> hash on the X710 which by all means is the future of the IDS and has
> a good chance of becoming a gold standard.
> 
> There was a path sent by a Suricata developer Victor Julien a while
> ago. Can go get back to that discussion?


-- 
Cooper Nelson
Network Security Analyst
UCSD ITS Security Team
cn...@uc... x41042