[Desmume-cvs] desmume/src armcpu.c, 1.11, 1.12 armcpu.h, 1.19, 1.20 thumb_instructions.c, 1.7, 1.8

[shash <sha...@us...>]

Update of /cvsroot/desmume/desmume/src
In directory sc8-pr-cvs12.sourceforge.net:/tmp/cvs-serv16450

Modified Files:
	armcpu.c armcpu.h thumb_instructions.c 
Log Message:
- Patch #1810861 by carlo_bramini

Index: thumb_instructions.c
===================================================================
RCS file: /cvsroot/desmume/desmume/src/thumb_instructions.c,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -d -r1.7 -r1.8
--- thumb_instructions.c	19 Oct 2007 09:31:53 -0000	1.7
+++ thumb_instructions.c	28 Oct 2007 16:43:13 -0000	1.8
@@ -868,7 +868,7 @@
 static u32 FASTCALL OP_B_COND(armcpu_t *cpu)
 {
      u32 i = cpu->instruction;
-     if(!TEST_COND((i>>8)&0xF, cpu->CPSR))
+     if(!TEST_COND((i>>8)&0xF, 0, cpu->CPSR))
           return 1;
      
      cpu->R[15] += ((s32)((s8)(i&0xFF)))<<1;

Index: armcpu.c
===================================================================
RCS file: /cvsroot/desmume/desmume/src/armcpu.c,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -d -r1.11 -r1.12
--- armcpu.c	19 Oct 2007 09:31:53 -0000	1.11
+++ armcpu.c	28 Oct 2007 16:43:13 -0000	1.12
@@ -26,6 +26,57 @@
 #include <stdlib.h>
 #include <stdio.h>
 
+const unsigned char arm_cond_table[16*16] = {
+    /* N=0, Z=0, C=0, V=0 */
+    0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,
+    0x00,0xFF,0xFF,0x00,0xFF,0x00,0xFF,0x20,
+    /* N=0, Z=0, C=0, V=1 */
+    0x00,0xFF,0x00,0xFF,0x00,0xFF,0xFF,0x00,
+    0x00,0xFF,0x00,0xFF,0x00,0xFF,0xFF,0x20,
+    /* N=0, Z=0, C=1, V=0 */
+    0x00,0xFF,0xFF,0x00,0x00,0xFF,0x00,0xFF,
+    0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x20,
+    /* N=0, Z=0, C=1, V=1 */
+    0x00,0xFF,0xFF,0x00,0x00,0xFF,0xFF,0x00,
+    0xFF,0x00,0x00,0xFF,0x00,0xFF,0xFF,0x20,
+    /* N=0, Z=1, C=0, V=0 */
+    0xFF,0x00,0x00,0xFF,0x00,0xFF,0x00,0xFF,
+    0x00,0xFF,0xFF,0x00,0x00,0xFF,0xFF,0x20,
+    /* N=0, Z=1, C=0, V=1 */
+    0xFF,0x00,0x00,0xFF,0x00,0xFF,0xFF,0x00,
+    0x00,0xFF,0x00,0xFF,0x00,0xFF,0xFF,0x20,
+    /* N=0, Z=1, C=1, V=0 */
+    0xFF,0x00,0xFF,0x00,0x00,0xFF,0x00,0xFF,
+    0x00,0xFF,0xFF,0x00,0x00,0xFF,0xFF,0x20,
+    /* N=0, Z=1, C=1, V=1 */
+    0xFF,0x00,0xFF,0x00,0x00,0xFF,0xFF,0x00,
+    0x00,0xFF,0x00,0xFF,0x00,0xFF,0xFF,0x20,
+    /* N=1, Z=0, C=0, V=0 */
+    0x00,0xFF,0x00,0xFF,0xFF,0x00,0x00,0xFF,
+    0x00,0xFF,0x00,0xFF,0x00,0xFF,0xFF,0x20,
+    /* N=1, Z=0, C=0, V=1 */
+    0x00,0xFF,0x00,0xFF,0xFF,0x00,0xFF,0x00,
+    0x00,0xFF,0xFF,0x00,0xFF,0x00,0xFF,0x20,
+    /* N=1, Z=0, C=1, V=0 */
+    0x00,0xFF,0xFF,0x00,0xFF,0x00,0x00,0xFF,
+    0xFF,0x00,0x00,0xFF,0x00,0xFF,0xFF,0x20,
+    /* N=1, Z=0, C=1, V=1 */
+    0x00,0xFF,0xFF,0x00,0xFF,0x00,0xFF,0x00,
+    0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x20,
+    /* N=1, Z=1, C=0, V=0 */
+    0xFF,0x00,0x00,0xFF,0xFF,0x00,0x00,0xFF,
+    0x00,0xFF,0x00,0xFF,0x00,0xFF,0xFF,0x20,
+    /* N=1, Z=1, C=0, V=1 */
+    0xFF,0x00,0x00,0xFF,0xFF,0x00,0xFF,0x00,
+    0x00,0xFF,0xFF,0x00,0x00,0xFF,0xFF,0x20,
+    /* N=1, Z=1, C=1, V=0 */
+    0xFF,0x00,0xFF,0x00,0xFF,0x00,0x00,0xFF,
+    0x00,0xFF,0x00,0xFF,0x00,0xFF,0xFF,0x20,
+    /* N=1, Z=1, C=1, V=1 */
+    0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,
+    0x00,0xFF,0xFF,0x00,0x00,0xFF,0xFF,0x20,
+};
+
 armcpu_t NDS_ARM7;
 armcpu_t NDS_ARM9;
 
@@ -496,7 +547,8 @@
 
 	if(armcpu->CPSR.bits.T == 0)
 	{
-		if((TEST_COND(CONDITION(armcpu->instruction), armcpu->CPSR)) || ((CONDITION(armcpu->instruction)==0xF)&&(CODE(armcpu->instruction)==0x5)))
+/*        if((TEST_COND(CONDITION(armcpu->instruction), armcpu->CPSR)) || ((CONDITION(armcpu->instruction)==0xF)&&(CODE(armcpu->instruction)==0x5)))*/
+        if((TEST_COND(CONDITION(armcpu->instruction), CODE(armcpu->instruction), armcpu->CPSR)))
 		{
 			c += arm_instructions_set[INSTRUCTION_INDEX(armcpu->instruction)](armcpu);
 		}

Index: armcpu.h
===================================================================
RCS file: /cvsroot/desmume/desmume/src/armcpu.h,v
retrieving revision 1.19
retrieving revision 1.20
diff -u -d -r1.19 -r1.20
--- armcpu.h	19 Oct 2007 09:31:53 -0000	1.19
+++ armcpu.h	28 Oct 2007 16:43:13 -0000	1.20
@@ -69,6 +69,7 @@
 #define LE	0xD
 #define AL	0xE	
 
+/*
 #define TEST_COND(cond, CPSR)	(((cond)==AL) ||\
 					 (((cond)==EQ) && ( CPSR.bits.Z))||\
 					 (((cond)==NE) && (!CPSR.bits.Z))||\
@@ -84,6 +85,11 @@
 					 (((cond)==LT) && (CPSR.bits.N!=CPSR.bits.V))||\
 					 (((cond)==GT) && (CPSR.bits.Z==0) && (CPSR.bits.N==CPSR.bits.V))||\
 					 (((cond)==LE) && ((CPSR.bits.Z) || (CPSR.bits.N!=CPSR.bits.V))))
+*/
+
+extern const unsigned char arm_cond_table[16*16];
+
+#define TEST_COND(cond, inst, CPSR)   ((arm_cond_table[((CPSR.val >> 24) & 0xf0)+(cond)] >> (inst)) & 1)
 
 
 enum Mode