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[Desmume-cvs] desmume/src memory.c, 1.1, 1.2 memory.h, 1.1, 1.2 types.h, 1.7, 1.8
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From: thoduv <th...@us...> - 2006-07-04 23:43:52
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Update of /cvsroot/desmume/desmume/src In directory sc8-pr-cvs4.sourceforge.net:/tmp/cvs-serv16419 Modified Files: memory.c memory.h types.h Log Message: New memory system update (endian-safe). Index: types.h =================================================================== RCS file: /cvsroot/desmume/desmume/src/types.h,v retrieving revision 1.7 retrieving revision 1.8 diff -u -d -r1.7 -r1.8 --- types.h 4 Jul 2006 21:48:58 -0000 1.7 +++ types.h 4 Jul 2006 23:43:48 -0000 1.8 @@ -107,6 +107,10 @@ # define LOCAL_TO_LE_32(x) (x) #endif +/* kilobytes and megabytes macro */ +#define MB(x) ((x)*1024*1024) +#define KB(x) ((x)*1024) + typedef enum { ARM9 = 0, Index: memory.c =================================================================== RCS file: /cvsroot/desmume/desmume/src/memory.c,v retrieving revision 1.1 retrieving revision 1.2 diff -u -d -r1.1 -r1.2 --- memory.c 4 Jul 2006 20:46:23 -0000 1.1 +++ memory.c 4 Jul 2006 23:43:48 -0000 1.2 @@ -1,82 +1,274 @@ #include "memory.h" -static u8 zero_read() { return 0; } -static u8 zero_read16() { return 0; } -static u8 zero_read32() { return 0; } +#if 0 /* example */ +static u8 mainram9_read8(u32 addr) +{ + return 0; +} +static u16 mainram9_read16(u32 addr) +{ + return 0; +} +static u32 mainram9_read32(u32 addr) +{ + return 0; +} -static u8 zero_write8() { ; } -static u8 zero_write16() { ; } -static u8 zero_write32() { ; } +static void mainram9_write8(u32 addr, u8 val) +{ +} +static void mainram9_write16(u32 addr, u16 val) +{ +} +static void mainram9_write32(u32 addr, u32 val) +{ +} +#endif +/******************************* GLOBAL MEMORY STRUCT *******************************/ -const mem_zone_fn_t mem_zones_fn[2][0x10] = +nds_mem_t nds_mem; + + +/******************************* ARM9 MEMORY HANDLERS *******************************/ + +/*************** zero: unhandled memory ***************/ + +static u8 zero9_read8(u32 addr) { LOG("ARM9 read8 to unhandled memory: *%08X\n", addr); return 0; } +static u16 zero9_read16(u32 addr) { LOG("ARM9 read16 to unhandled memory: *%08X\n", addr); return 0; } +static u32 zero9_read32(u32 addr) { LOG("ARM9 read32 to unhandled memory: *%08X\n", addr); return 0; } + +static void zero9_write8(u32 addr, u8 val) { LOG("ARM9 write8 to unhandled memory: *%08X = %02X\n", addr, val); } +static void zero9_write16(u32 addr, u16 val) { LOG("ARM9 write16 to unhandled memory: *%08X = %04X\n", addr, val); } +static void zero9_write32(u32 addr, u32 val) { LOG("ARM9 write32 to unhandled memory: *%08X = %08X\n", addr, val); } + + +/******************************* ARM7 MEMORY HANDLERS *******************************/ + +/*************** zero: unhandled memory ***************/ + +static u8 zero7_read8(u32 addr) { LOG("ARM7 read8 to unhandled memory: *%08X\n", addr); return 0; } +static u16 zero7_read16(u32 addr) { LOG("ARM7 read16 to unhandled memory: *%08X\n", addr); return 0; } +static u32 zero7_read32(u32 addr) { LOG("ARM7 read32 to unhandled memory: *%08X\n", addr); return 0; } + +static void zero7_write8(u32 addr, u8 val) { LOG("ARM7 write8 to unhandled memory: *%08X = %02X\n", addr, val); } +static void zero7_write16(u32 addr, u16 val) { LOG("ARM7 write16 to unhandled memory: *%08X = %04X\n", addr, val); } +static void zero7_write32(u32 addr, u32 val) { LOG("ARM7 write32 to unhandled memory: *%08X = %08X\n", addr, val); } + +/*************** NDS7_MEMBASE_WRAM: arm7's own wram ***************/ +/* TODO: handle correctly splitting of shared ram */ + +static u8 shared7_wram7_read8(u32 addr) { + if(NDS7_MEM_IS_WRAM(addr)) /* check if we're in in arm7 wram */ { - {zero_read8, zero_read16, zero_read32, zero_write8, zero_write16, zero_write32}, - {zero_read8, zero_read16, zero_read32, zero_write8, zero_write16, zero_write32}, - {zero_read8, zero_read16, zero_read32, zero_write8, zero_write16, zero_write32}, - {zero_read8, zero_read16, zero_read32, zero_write8, zero_write16, zero_write32}, - {zero_read8, zero_read16, zero_read32, zero_write8, zero_write16, zero_write32}, - {zero_read8, zero_read16, zero_read32, zero_write8, zero_write16, zero_write32}, - {zero_read8, zero_read16, zero_read32, zero_write8, zero_write16, zero_write32}, - {zero_read8, zero_read16, zero_read32, zero_write8, zero_write16, zero_write32}, - {zero_read8, zero_read16, zero_read32, zero_write8, zero_write16, zero_write32}, - {zero_read8, zero_read16, zero_read32, zero_write8, zero_write16, zero_write32}, - {zero_read8, zero_read16, zero_read32, zero_write8, zero_write16, zero_write32}, - {zero_read8, zero_read16, zero_read32, zero_write8, zero_write16, zero_write32}, - {zero_read8, zero_read16, zero_read32, zero_write8, zero_write16, zero_write32}, - {zero_read8, zero_read16, zero_read32, zero_write8, zero_write16, zero_write32}, - {zero_read8, zero_read16, zero_read32, zero_write8, zero_write16, zero_write32}, - {zero_read8, zero_read16, zero_read32, zero_write8, zero_write16, zero_write32}, + return MEM_8(nds_mem.arm7_mem.wram, addr & NDS7_MEMMASK_WRAM); } + else /* or in shared ram */ { - {zero_read8, zero_read16, zero_read32, zero_write8, zero_write16, zero_write32}, - {zero_read8, zero_read16, zero_read32, zero_write8, zero_write16, zero_write32}, - {zero_read8, zero_read16, zero_read32, zero_write8, zero_write16, zero_write32}, - {zero_read8, zero_read16, zero_read32, zero_write8, zero_write16, zero_write32}, - {zero_read8, zero_read16, zero_read32, zero_write8, zero_write16, zero_write32}, - {zero_read8, zero_read16, zero_read32, zero_write8, zero_write16, zero_write32}, - {zero_read8, zero_read16, zero_read32, zero_write8, zero_write16, zero_write32}, - {zero_read8, zero_read16, zero_read32, zero_write8, zero_write16, zero_write32}, - {zero_read8, zero_read16, zero_read32, zero_write8, zero_write16, zero_write32}, - {zero_read8, zero_read16, zero_read32, zero_write8, zero_write16, zero_write32}, - {zero_read8, zero_read16, zero_read32, zero_write8, zero_write16, zero_write32}, - {zero_read8, zero_read16, zero_read32, zero_write8, zero_write16, zero_write32}, - {zero_read8, zero_read16, zero_read32, zero_write8, zero_write16, zero_write32}, - {zero_read8, zero_read16, zero_read32, zero_write8, zero_write16, zero_write32}, - {zero_read8, zero_read16, zero_read32, zero_write8, zero_write16, zero_write32}, - {zero_read8, zero_read16, zero_read32, zero_write8, zero_write16, zero_write32}, + return MEM_8(nds_mem.sharedram, addr & NDS_MEMMASK_SHAREDRAM); + } +} +static u16 shared7_wram7_read16(u32 addr) +{ + if(NDS7_MEM_IS_WRAM(addr)) /* check if we're in in arm7 wram */ + { + return MEM_16(nds_mem.arm7_mem.wram, addr & NDS7_MEMMASK_WRAM); + } + else /* or in shared ram */ + { + return MEM_16(nds_mem.sharedram, addr & NDS_MEMMASK_SHAREDRAM); + } +} +static u32 shared7_wram7_read32(u32 addr) +{ + if(NDS7_MEM_IS_WRAM(addr)) /* check if we're in in arm7 wram */ + { + return MEM_32(nds_mem.arm7_mem.wram, addr & NDS7_MEMMASK_WRAM); + } + else /* or in shared ram */ + { + return MEM_32(nds_mem.sharedram, addr & NDS_MEMMASK_SHAREDRAM); + } +} + +static void shared7_wram7_write8(u32 addr, u8 val) +{ + if(NDS7_MEM_IS_WRAM(addr)) /* check if we're in in arm7 wram */ + { + MEM_8(nds_mem.arm7_mem.wram, addr & NDS7_MEMMASK_WRAM) = val; + } + else /* or in shared ram */ + { + MEM_8(nds_mem.sharedram, addr & NDS_MEMMASK_SHAREDRAM) = val; + } +} +static void shared7_wram7_write16(u32 addr, u16 val) +{ + if(NDS7_MEM_IS_WRAM(addr)) /* check if we're in in arm7 wram */ + { + MEM_16(nds_mem.arm7_mem.wram, addr & NDS7_MEMMASK_WRAM) = val; + } + else /* or in shared ram */ + { + MEM_16(nds_mem.sharedram, addr & NDS_MEMMASK_SHAREDRAM) = val; + } +} +static void shared7_wram7_write32(u32 addr, u32 val) +{ + if(NDS7_MEM_IS_WRAM(addr)) /* check if we're in in arm7 wram */ + { + MEM_32(nds_mem.arm7_mem.wram, addr & NDS7_MEMMASK_WRAM) = val; + } + else /* or in shared ram */ + { + MEM_32(nds_mem.sharedram, addr & NDS_MEMMASK_SHAREDRAM) = val; } } +/******************************* COMMON MEMORY HANDLERS *******************************/ + +/*************** NDS9_MEMBASE_MAINRAM, NDS7_MEMBASE_MAINRAM: main memory ***************/ + +static u8 mainram_read8(u32 addr) +{ + return MEM_8(nds_mem.mainram, addr & NDS_MEMMASK_MAINRAM); +} +static u16 mainram_read16(u32 addr) +{ + return MEM_16(nds_mem.mainram, addr & NDS_MEMMASK_MAINRAM); +} +static u32 mainram_read32(u32 addr) +{ + return MEM_32(nds_mem.mainram, addr & NDS_MEMMASK_MAINRAM); +} + +static void mainram_write8(u32 addr, u8 val) +{ + MEM_8(nds_mem.mainram, addr & NDS_MEMMASK_MAINRAM) = val; +} +static void mainram_write16(u32 addr, u16 val) +{ + MEM_16(nds_mem.mainram, addr & NDS_MEMMASK_MAINRAM) = val; +} +static void mainram_write32(u32 addr, u32 val) +{ + MEM_32(nds_mem.mainram, addr & NDS_MEMMASK_MAINRAM) = val; +} + + +/******************************* MEMORY REGIONS DEFINITIONS (+ HANDLERS TABLE) *******************************/ + +const mem_region_t mem_regions[2][0x10] = +{ + /*************** ARM9 ***************/ + { + {zero9_read8, zero9_read16, zero9_read32, zero9_write8, zero9_write16, zero9_write32}, /**/ + {zero9_read8, zero9_read16, zero9_read32, zero9_write8, zero9_write16, zero9_write32}, /**/ + {mainram_read8, mainram_read16, mainram_read32, mainram_write8, mainram_write16, mainram_write32}, /* NDS9_MEMBASE_MAINRAM */ + {zero9_read8, zero9_read16, zero9_read32, zero9_write8, zero9_write16, zero9_write32}, /**/ + {zero9_read8, zero9_read16, zero9_read32, zero9_write8, zero9_write16, zero9_write32}, /**/ + {zero9_read8, zero9_read16, zero9_read32, zero9_write8, zero9_write16, zero9_write32}, /**/ + {zero9_read8, zero9_read16, zero9_read32, zero9_write8, zero9_write16, zero9_write32}, /**/ + {zero9_read8, zero9_read16, zero9_read32, zero9_write8, zero9_write16, zero9_write32}, /**/ + {zero9_read8, zero9_read16, zero9_read32, zero9_write8, zero9_write16, zero9_write32}, /**/ + {zero9_read8, zero9_read16, zero9_read32, zero9_write8, zero9_write16, zero9_write32}, /**/ + {zero9_read8, zero9_read16, zero9_read32, zero9_write8, zero9_write16, zero9_write32}, /**/ + {zero9_read8, zero9_read16, zero9_read32, zero9_write8, zero9_write16, zero9_write32}, /**/ + {zero9_read8, zero9_read16, zero9_read32, zero9_write8, zero9_write16, zero9_write32}, /**/ + {zero9_read8, zero9_read16, zero9_read32, zero9_write8, zero9_write16, zero9_write32}, /**/ + {zero9_read8, zero9_read16, zero9_read32, zero9_write8, zero9_write16, zero9_write32}, /**/ + {zero9_read8, zero9_read16, zero9_read32, zero9_write8, zero9_write16, zero9_write32}, /**/ + }, + /*************** ARM7 ***************/ + { + {zero7_read8, zero7_read16, zero7_read32, zero7_write8, zero7_write16, zero7_write32}, /**/ + {zero7_read8, zero7_read16, zero7_read32, zero7_write8, zero7_write16, zero7_write32}, /**/ + {mainram_read8, mainram_read16, mainram_read32, mainram_write8, mainram_write16, mainram_write32}, /* NDS7_MEMBASE_MAINRAM */ + {shared7_wram7_read8, shared7_wram7_read16, shared7_wram7_read32, shared7_wram7_write8, shared7_wram7_write16, shared7_wram7_write32}, /* NDS7_MEMBASE_SHAREDRAM_WRAM */ + {zero7_read8, zero7_read16, zero7_read32, zero7_write8, zero7_write16, zero7_write32}, /**/ + {zero7_read8, zero7_read16, zero7_read32, zero7_write8, zero7_write16, zero7_write32}, /**/ + {zero7_read8, zero7_read16, zero7_read32, zero7_write8, zero7_write16, zero7_write32}, /**/ + {zero7_read8, zero7_read16, zero7_read32, zero7_write8, zero7_write16, zero7_write32}, /**/ + {zero7_read8, zero7_read16, zero7_read32, zero7_write8, zero7_write16, zero7_write32}, /**/ + {zero7_read8, zero7_read16, zero7_read32, zero7_write8, zero7_write16, zero7_write32}, /**/ + {zero7_read8, zero7_read16, zero7_read32, zero7_write8, zero7_write16, zero7_write32}, /**/ + {zero7_read8, zero7_read16, zero7_read32, zero7_write8, zero7_write16, zero7_write32}, /**/ + {zero7_read8, zero7_read16, zero7_read32, zero7_write8, zero7_write16, zero7_write32}, /**/ + {zero7_read8, zero7_read16, zero7_read32, zero7_write8, zero7_write16, zero7_write32}, /**/ + {zero7_read8, zero7_read16, zero7_read32, zero7_write8, zero7_write16, zero7_write32}, /**/ + {zero7_read8, zero7_read16, zero7_read32, zero7_write8, zero7_write16, zero7_write32}, /**/ + } +}; + + +/******************************* MEMORY WRITE/READ FUNCTIONS *******************************/ + u8 mem_read8(cpu_id_t cpu, u32 addr) { - return mem_zones_fn[cpu][((addr >> 24) & 4)].read8(addr); + return mem_regions[cpu][((addr >> 24) & 0xF)].read8(addr); } u16 mem_read16(cpu_id_t cpu, u32 addr) { - return mem_zones_fn[cpu][((addr >> 24) & 4)].read16(addr); + u16 val = mem_regions[cpu][((addr >> 24) & 0xF)].read16(addr); + return LE_TO_LOCAL_16(val); } u32 mem_read32(cpu_id_t cpu, u32 addr) { - return mem_zones_fn[cpu][((addr >> 24) & 4)].read32(addr); + u32 val = mem_regions[cpu][((addr >> 24) & 0xF)].read32(addr); + return LE_TO_LOCAL_32(val); } void mem_write8(cpu_id_t cpu, u32 addr, u8 val) { - mem_zones_fn[cpu][((addr >> 24) & 4)].write8(addr, val); + mem_regions[cpu][((addr >> 24) & 0xF)].write8(addr, val); } void mem_write16(cpu_id_t cpu, u32 addr, u16 val) { - mem_zones_fn[cpu][((addr >> 24) & 4)].write16(addr, val); + mem_regions[cpu][((addr >> 24) & 0xF)].write16(addr, LOCAL_TO_LE_16(val)); } void mem_write32(cpu_id_t cpu, u32 addr, u32 val) { - mem_zones_fn[cpu][((addr >> 24) & 4)].write32(addr, val); + mem_regions[cpu][((addr >> 24) & 0xF)].write32(addr, LOCAL_TO_LE_32(val)); } +/**************************************************************/ + +#ifdef _TEST_MAIN_ +#define OK(a,b) ((a==b)?"ok!":"error, awaiting " #b "...") +int main(int argc, char *argv[]) +{ + u32 tmp; + + mem_write32(ARM9, 0x02000000, 0x12345678); + tmp = mem_read32(ARM9, 0x02000000); + LOG("%08X, %s\n", tmp, OK(tmp, 0x12345678)); + + tmp = mem_read8(ARM9, 0x02000000); + LOG("%02X, %s\n", tmp, OK(tmp, 0x78)); + + tmp = mem_read16(ARM9, 0x02000002); + LOG("%04X, %s\n", tmp, OK(tmp, 0x1234)); + + mem_write32(ARM7, 0x03800000, 0x11); + tmp = mem_read32(ARM7, 0x03800000); + LOG("%08X, %s\n", tmp, OK(tmp, 0x11)); + + mem_write32(ARM7, 0x037fffff, 0x22); + tmp = mem_read32(ARM7, 0x037fffff); + LOG("%08X, %s\n", tmp, OK(tmp, 0x22)); + + return 0; +} +#endif + + + + + + Index: memory.h =================================================================== RCS file: /cvsroot/desmume/desmume/src/memory.h,v retrieving revision 1.1 retrieving revision 1.2 diff -u -d -r1.1 -r1.2 --- memory.h 4 Jul 2006 20:46:23 -0000 1.1 +++ memory.h 4 Jul 2006 23:43:48 -0000 1.2 @@ -3,62 +3,120 @@ #include "types.h" -enum +#ifdef _TEST_MAIN_ +# include <stdio.h> +# define LOG(...) fprintf(stderr, __VA_ARGS__); +#endif + +/******************************* MEM ACCESS MACROS *******************************/ + +#define MEM_8(m,a) (((u8*)(m))[(a)]) +#define MEM_16(m,a) (((u16*)(m))[(a)>>1]) +#define MEM_32(m,a) (((u32*)(m))[(a)>>2]) + + +/******************************* ARM9 MEMORY DEFINITION *******************************/ + +enum /* fixed arm9 memory regions (dtcm's base adress is defined by cp15) */ { - NDS9_MEM_NOTHING = 0x0, - NDS9_MEM_ITCM = 0x1, - NDS9_MEM_MAINRAM = 0x2, - NDS9_MEM_SHAREDRAM = 0x3, - NDS9_MEM_IO = 0x4, - NDS9_MEM_VRAMPAL = 0x5, - NDS9_MEM_VRAMBG = 0x6, - NDS9_MEM_VRAMOAM = 0x7, - NDS9_MEM_GBAROM_0 = 0x8, - NDS9_MEM_GBAROM_1 = 0x9, - NDS9_MEM_GBASRAM_0 = 0xA, - NDS9_MEM_GBASRAM_1 = 0xB, - NDS9_MEM_GBASRAM_2 = 0xC, - NDS9_MEM_GBASRAM_3 = 0xD, - NDS9_MEM_GBASRAM_4 = 0xE, - NDS9_MEM_BIOS = 0xF -} + NDS9_MEMBASE_ITCM = 0x1, + NDS9_MEMBASE_MAINRAM = 0x2, + NDS9_MEMBASE_SHAREDRAM = 0x3, + NDS9_MEMBASE_IO = 0x4, + NDS9_MEMBASE_VRAMPAL = 0x5, + NDS9_MEMBASE_VRAMBG = 0x6, + NDS9_MEMBASE_VRAMOAM = 0x7, + NDS9_MEMBASE_GBAROM_0 = 0x8, + NDS9_MEMBASE_GBAROM_1 = 0x9, + NDS9_MEMBASE_GBASRAM = 0xA, + NDS9_MEMBASE_BIOS = 0xF +}; -enum +typedef struct { - NDS7_MEM_BIOS = 0x0, - NDS7_MEM_MAINRAM = 0x2, - NDS7_MEM_SHAREDRAM = 0x3, - NDS7_MEM_IO = 0x4, - NDS7_MEM_VRAMARM7 = 0x6, - NDS7_MEM_GBAROM_0 = 0x8, - NDS7_MEM_GBAROM_1 = 0x9, - NDS7_MEM_GBASRAM_0 = 0xA, - NDS7_MEM_GBASRAM_1 = 0xB, - NDS7_MEM_GBASRAM_2 = 0xC, - NDS7_MEM_GBASRAM_3 = 0xD, - NDS7_MEM_GBASRAM_4 = 0xE, -} + u8 itcm[KB(32)]; /* instruction tcm (inside arm9 itself) */ + u8 dtcm[KB(16)]; /* data tcm (idem) */ + u32 dtcm_base; /* base adress for dtcm */ +} arm9_mem_t; -typedef u8 (*mem_read8_t)(cpu_id_t cpu, u32 addr); -typedef u16 (*mem_read16_t)(cpu_id_t cpu, u32 addr); -typedef u32 (*mem_read32_t)(cpu_id_t cpu, u32 addr); -typedef void (*mem_write8_t)(cpu_id_t cpu, u32 addr, u8 val); -typedef void (*mem_write16_t)(cpu_id_t cpu, u32 addr, u16 val); -typedef void (*mem_write32_t)(cpu_id_t cpu, u32 addr, u32 val); +/******************************* ARM7 MEMORY DEFINITION *******************************/ + +#define NDS7_MEM_IS_WRAM(a) ((a)>=0x03800000) + +enum /* masks for memory adresses */ +{ + NDS7_MEMMASK_WRAM = 0xFFFF +}; + +enum /* arm7 memory regions */ +{ + NDS7_MEMBASE_BIOS = 0x0, + NDS7_MEMBASE_MAINRAM = 0x2, + NDS7_MEMBASE_SHAREDRAM_WRAM = 0x3, + NDS7_MEMBASE_IO = 0x4, + NDS7_MEMBASE_VRAMARM7 = 0x6, + NDS7_MEMBASE_GBAROM_0 = 0x8, + NDS7_MEMBASE_GBAROM_1 = 0x9, + NDS7_MEMBASE_GBASRAM = 0xA, +}; typedef struct { - mem_read_8_t *read8; - mem_read_16_t *read16; - mem_read_32_t *read32; + u8 wram[KB(64)]; /* arm7's own wram */ +} arm7_mem_t; + + +/******************************* GLOBAL MEMORY DEFINITION *******************************/ + +enum /* masks for memory adresses */ +{ + NDS_MEMMASK_MAINRAM = 0xFFFFFF, + NDS_MEMMASK_SHAREDRAM = 0xFFF, +}; + +typedef struct +{ + u8 mainram[MB(4)]; /* nds' main ram (accesible by both cpu) */ + u8 sharedram[KB(32)]; /* shared ram, splitted between both cpu, controled via a register */ - mem_write_8_t *write8; - mem_write_16_t *write16; - mem_write_32_t *write32; -} mem_zone_fn_t; + u8 *gbarom; /* gba slot rom memory */ + + arm7_mem_t arm7_mem; /* arm7 memory */ + arm9_mem_t arm9_mem; /* arm9 memory */ +} nds_mem_t; -extern const mem_zone_fn_t *mem_zones_fn[2][0x10]; + +/******************************* MEMORY REGIONS STRUCTURE *******************************/ + +typedef u8 (*mem_read8_t)(u32 addr); +typedef u16 (*mem_read16_t)(u32 addr); +typedef u32 (*mem_read32_t)(u32 addr); + +typedef void (*mem_write8_t)(u32 addr, u8 val); +typedef void (*mem_write16_t)(u32 addr, u16 val); +typedef void (*mem_write32_t)(u32 addr, u32 val); + +typedef struct /* defines a memory region */ +{ + mem_read8_t read8; + mem_read16_t read16; + mem_read32_t read32; + + mem_write8_t write8; + mem_write16_t write16; + mem_write32_t write32; +} mem_region_t; + + +/******************************* GLOBAL VARIABLES *******************************/ + +extern const mem_region_t mem_region[2][0x10]; /* nds's memory regions */ + +extern nds_mem_t nds_mem; + + +/******************************* READ/WRITE FUNCTIONS *******************************/ u8 mem_read8(cpu_id_t cpu, u32 addr); u16 mem_read16(cpu_id_t cpu, u32 addr); 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