When Verilog code makes a hierarchical reference that
requires upward name referencing, Covered displays an
error that says that we are doing invalid hierarchical
referencing.
This bug is fixed in CVS and will be available in the 0.4.6
stable release. Covered now conforms to the upwards name
referencing description in the LRM and matches both VCS and
Icarus Verilog.
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This bug is fixed in CVS and will be available in the 0.4.6
stable release. Covered now conforms to the upwards name
referencing description in the LRM and matches both VCS and
Icarus Verilog.