#83 misparsing of labelled empty blocks inside case

[Anonymous]

Hi
I'm fairly sure this testcase shows a problem in
covered's parser (cver accepts it as valid)

Also, I found that fairly minor breakages in the syntax
would cause covered to loop or to segv. For example,
swapping the two cases below causes a loop. (I'm afraid
I can't reproduce the segv - sorry - but I will email
the core file to you.)

Cheers
Ed
ed.spittles at artofsilicon.com

Covered covered-0.4.5 -- Verilog Code Coverage Utility
Written by Trevor Williams (trevorw@charter.net)
Freely distributable under the GPL license

Reading design...
Parsing file 'covered-tc-9.v'
ERROR! syntax error, unexpected NUMBER, expecting
K_end, file: covered-tc-9.v, line: 37
ERROR! Illegal statement, file: covered-tc-9.v, line: 39
ERROR! Error in parsing design

module x_m (
input ip
);

wire [31:0]
x_w;

reg [3:0] x_r;

always @*
begin : x_add_l

reg [31:0] x_add_r;

case (x_r)
  4'b0001:
    begin : label1
    end
  4'b0000:
    begin
       x_add_r[31:0] = x_w;
    end
endcase

end

endmodule

[Trevor Williams]

Logged In: YES
user_id=512771

I have submitted a fix for this issue that is available in
the covered-0_4_5-branch branch in CVS. I believe that it
will take care of all issues regarding this coding style;
however, please update this bug report if this is not the
case. The general public will see this in the 0.4.6 stable
release.

[Nobody/Anonymous]

Logged In: NO

thanks!
Ed

[Nobody/Anonymous]

Logged In: NO

thanks!
Ed

[Trevor Williams]

Logged In: YES
user_id=512771

Closing this bug as it should be fixed in the 0.4.6 stable
release now.