#306 define to nothing not working as expected
The attached code demonstrates an issue with covered related to a `define with no value.
I specify gate delays as define GD #0.1 to allow easier debug. Then to make sure the delays are not causing the circuit to work when it shouldn't I change the define to bedefine GD. It appears that covered is giving the define some value instead of just being nothing. The example shown is producing an empty file, but my real code produces a file that often has missed cases and under some setting seems to produce a completely valid and completely scored design. I'm not sure how that's happening and at the moment I don;t have a lot of free time so hopefully this simple report is enough to get everything working as needed. If not we can deal with the rest later.
example code
Attaching a patch that will fix this issue. I was incorrectly setting these type of defines to a value of 1. The fix will be generally available in the 0.7.8 stable release of Covered.
Bug fix patch
That appears to have fixed the problem. Covered now complains about coverage on a few lines, signals, but I believe that is because of some now zero width glitches created by the simulator. I'll look at these tomorrow to make sure. Thanks for the quick fix! This was a bit of a show stopper, the others can easily be worked around. I'm closing the report as fixed.
Attaching a second patch that also needs to be added to output the correct coverage information in reports. This fix was missing from the first patch. As always, this patch will be generally available in the 0.7.8 stable release.
Cary,
Just as an FYI, Covered currently will execute any code in the replication even if the multiplier is a value of 0. I've been following the Icarus Verilog thread on this issue. I believe that the specification stated that function calls/system calls/etc. should be executed even if the multiplier is a value of 0.
If you believe this behavior is incorrect and should be fixed, let me know.
Thanks,
Trevor