#296 verilog parenthesis parsing segfault

[AKR]

$ gdb covered
GNU gdb 6.8
Cadence modification version 4.8.2 - 09/2009
Copyright (C) 2008 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later http://gnu.org/licenses/gpl.html
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law. Type "show copying"
and "show warranty" for details.
This GDB was configured as "x86_64-pc-linux-gnu"...
(gdb) run score -vpi -g 2 -t test -v test.v -o test.cdd
Starting program: covered score -vpi -g 2 -t test -v test.v -o test.cdd

Covered covered-0.7.6 -- Verilog Code Coverage Utility
Written by Trevor Williams (phase1geo@gmail.com)
Freely distributable under the GPL license

Reading design...
Parsing file 'test.v'
WARNING! Removing logic block containing line 17 in file test.v because
it contains an unsupported system function
WARNING! Removing logic block containing line 20 in file test.v because
it contains an unsupported system function
WARNING! Removing logic block containing line 28 in file test.v because
it contains an unsupported system function

Program received signal SIGSEGV, Segmentation fault.
0x00000000004055bd in VLparse () at ./parser.y:2341
2341 $2->suppl.part.parenthesis = 1;
(gdb) quit

Problem and suggested fix

NOTE. Please check me on this. I am, by no means, a parser expert, but this looks fishy to me.

starting with line 2337 of parser.y:
| '(' expression ')'
{
/ if( ignore_mode == 0 ) { POSSIBLE PROBLEM - not checking if $2 is NULL. When this is added the Segfault disappears /
if( (ignore_mode == 0) && ($2 != NULL) ) {
$2->suppl.part.parenthesis = 1;
$$ = $2;
} else {
$$ = NULL;
}
}

Test code

`define Tms_min 10

module test ();

reg power_ready;
reg POR;
reg PPROG;
reg PWE;
time PTM_CHANGE;

initial begin
power_ready = 1'b1;
POR = 1'b0;
PPROG = 1'b0;
PWE = 1'b0;
PTM_CHANGE = $realtime;
#100;
POR = 1'b1;
PTM_CHANGE = $realtime;
#100;
$finish;

end

always @(posedge POR or posedge PPROG or posedge PWE)
begin
if(power_ready && ($realtime - PTM_CHANGE <`Tms_min) && PTM_CHANGE!=0 )
begin
$display($time," Timing Violation: PTM change Setup Time(Tms) is Illegal.");
end
end

endmodule // test

[Trevor Williams]

Bug fix patch

[Trevor Williams]

The proposed solution to this problem was the correct solution. The expression term should have been checked for NULL prior to being used. I have attached a patch for this bug which will also be generally available in the next stable release of Covered.

[SourceForge Robot]

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