#285 inline: warning about unsized numbers in concats

[Ed Spittles]

Hi Trevor
This is just a warning from verilator, but I expect you'll want to get everything warning-free.

$ verilator -cc "covered/verilog/test-unsized.v"
%Warning-WIDTHCONCAT: covered/verilog/test-unsized.v:49: Unsized numbers/parameters not allowed in concatenations.

where the instrumented code looks like
\covered$X26_36_36_2b003d = {0, a1005[1:0]};

Please find the testcase below (it isn't quite clean but does illustrate the problem)
Thanks
Ed

module a2000 (
input a2001 ,
input a2002
);
reg [15:0] a1000;
reg [4:0] a1001;
wire [2:0] a1005;
reg [7:0] a1002;
reg [7:0] a1003[63:1];
reg a1004[27:0];
always @*
begin : a2003
casez ( a1000 )
16'b???????????????1 :
begin
a1001 = 5'b0_0001;
end
16'b??????????????10 :
begin
a1001 = 5'b0_0010;
a1002 = a1003 [{ a1004 , 4'b0001}] + {6'd0, a1005 [1:0]};
end
endcase ;
end
endmodule

[Trevor Williams]

Attaching bug patch to fix this issue which will be generally available in CVS TOT and the next development release of Covered.

[Trevor Williams]

Bug fix patch

[SourceForge Robot]

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