Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory, combinational logic, FSM state/arc and assertion coverage report metrics viewable via GUI or ASCII format.

This project is ported to github and can be found at:
https://github.com/chiphackers/covered

Project Samples

Coverage analysis in progress

Project Activity

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Categories

Electronic Design Automation (EDA), Code Coverage

License

GNU General Public License version 2.0 (GPLv2)

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Additional Project Details

Languages

English

Intended Audience

Developers, Education

User Interface

Command-line, Tk

Programming Language

C, Tcl

Related Categories

C Electronic Design Automation (EDA) Software, C Code Coverage Tool, Tcl Electronic Design Automation (EDA) Software, Tcl Code Coverage Tool

Registered

2002-04-11
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