This project aim to develop a suite of tool to ease the development of ASIC/FPGA solution. The final program should be an IDE enabling the creation and specification of a project from it's start to finish.

Features

  • netlist extractor from edn for one chip
  • netlist to ucf creator

Project Activity

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Categories

Code Generators, Scientific/Engineering

License

MIT License

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Additional Project Details

Operating Systems

BSD, Linux, Windows

Intended Audience

Science/Research

User Interface

Command-line, Project is a templating system, Qt

Programming Language

C++, VHDL/Verilog

Related Categories

C++ Code Generators, C++ Scientific Engineering, VHDL/Verilog Code Generators, VHDL/Verilog Scientific Engineering

Registered

2008-11-25
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