BYU EDIF Tools Feature Requests

Brought to you by: andrewmkeller, brianpratt, derrickgw, ee320ta, and 3 others

Feature Requests Maximize Restore

# Sort A -> Z Sort Z -> A	Summary▾ Sort A -> Z Sort Z -> A	Milestone▾ Sort A -> Z Sort Z -> A Filter by Milestone	Status▾ Sort A -> Z Sort Z -> A Filter by Status	Owner▾ Sort A -> Z Sort Z -> A Filter by Owner	Created▾ Sort A -> Z Sort Z -> A	Updated▾ Sort A -> Z Sort Z -> A	Priority▾ Sort A -> Z Sort Z -> A
8	Output or document supported FPGA types	Next Release (example)	open	andrewmkeller	2016-10-14	2016-10-14	5
7	Automatically generate VHDL/Verilog templates	None	open		2009-07-10	2009-07-10	3
6	Modify JEdifTMRAnalysis to TMR bits from an array port	None	open		2009-02-25	2009-02-25	5
4	Add feature to vote more often in feedback loops	None	open		2008-12-08	2008-12-08	3
3	Improve run-time of JEdifCutset	None	open		2008-10-01	2008-10-01	5
2	Add regular expression functionality to "--tmr_i," "--tmr_c,	None	open		2008-09-22	2009-07-10	7
1	Provide utility/script to check for license in .java files	None	open		2008-05-21	2008-05-21	3

(applies to this page only)