Automatically generate VHDL/Verilog templates

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#7 Automatically generate VHDL/Verilog templates

Status: open

Owner: nobody

Labels: New Functionality (5)

Priority: 3

Updated: 2009-07-10

Created: 2009-07-10

Creator: Brian Pratt

Private: No

It would be nice if the tool could automatically generate a .vho file (like Xilinx does in Coregen) which includes text for the VHDL component declaration and instantiation of an EDIF file.

This could be included with the tools or a separate tool that works on any EDIF file.

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Brian Pratt - 2009-07-10

priority: 5 --> 3
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Automatically generate VHDL/Verilog templates

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#7 Automatically generate VHDL/Verilog templates

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