blob-cvs-commit — blob CVS commit messages list

CVS: blob/include/blob sa1100.h,1.2,1.3

[Christopher H. <ch...@us...>]

Update of /cvsroot/blob/blob/include/blob
In directory usw-pr-cvs1:/tmp/cvs-serv26723

Modified Files:
	sa1100.h 
Log Message:
our own sa1100.h (created from linux-2.5.26-rmk1); safe to include in assembly now (define __ASSEMBLY__); does not conflict with memsetup.h

Index: sa1100.h
===================================================================
RCS file: /cvsroot/blob/blob/include/blob/sa1100.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- sa1100.h	7 Nov 2001 12:25:03 -0000	1.2
+++ sa1100.h	25 Jul 2002 17:30:01 -0000	1.3
@@ -1,5 +1,6 @@
 /*
- * sa1100.h: wrapper file to include asm/arch-sa1100/SA-1100.h
+ * sa1100.h: Defines and macros for accessing the SA1100. Created from
+ * the kernel source.
  *
  * Copyright (C) 2001  Erik Mouw (J.A...@it...)
  *
@@ -24,11 +25,1860 @@
 #ifndef BLOB_SA1100_H
 #define BLOB_SA1100_H
 
[...1842 lines suppressed...]
+#define LCCR3_PixRsEdg	(LCCR3_PCP*0)	/*  Pixel clock Rising-Edge        */
+#define LCCR3_PixFlEdg	(LCCR3_PCP*1)	/*  Pixel clock Falling-Edge       */
+#define LCCR3_OEP	0x00800000	/* Output Enable Polarity (L_BIAS, */
+                	        	/* active display mode)            */
+#define LCCR3_OutEnH	(LCCR3_OEP*0)	/*  Output Enable active High      */
+#define LCCR3_OutEnL	(LCCR3_OEP*1)	/*  Output Enable active Low       */
+
+#define CPU_REVISION	(processor_id & 15)
+#define CPU_SA1110_A0	(0)
+#define CPU_SA1110_B0	(4)
+#define CPU_SA1110_B1	(5)
+#define CPU_SA1110_B2	(6)
+#define CPU_SA1110_B4	(8)
+
+#define CPU_SA1100_ID	(0x4401a110)
+#define CPU_SA1100_MASK	(0xfffffff0)
+#define CPU_SA1110_ID	(0x6901b110)
+#define CPU_SA1110_MASK	(0xfffffff0)
 
 #endif

CVS: blob/src/blob badge4.c,1.9,1.10

[Christopher H. <ch...@us...>]

Update of /cvsroot/blob/blob/src/blob
In directory usw-pr-cvs1:/tmp/cvs-serv26021

Modified Files:
	badge4.c 
Log Message:
more verbose startup

Index: badge4.c
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/badge4.c,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -d -r1.9 -r1.10
--- badge4.c	23 Jul 2002 20:06:44 -0000	1.9
+++ badge4.c	25 Jul 2002 17:27:51 -0000	1.10
@@ -89,7 +89,7 @@
 {
 	printf("\n\n\n" BOARD_NAME "\n"
 	       "Blob port by Christopher Hoover <ch...@hp...>.\n"
-	       "($Id$, " __DATE__ ")\n"
+	       "  (revision: $Revision$, built: " __DATE__ ")\n"
 	       "\n");
 }
 __initlist(badge4_banner, INIT_LEVEL_INITIAL_HARDWARE + 1);
@@ -136,6 +136,13 @@
 	int typ0, typ1;
 	int memory_type, row_bits, col_bits, module_rows, row_density;
 	u8 spd[128];
+
+	/* Disable memory bus/grant signals to avoid any suprious
+           memory requests */
+	PGSR &= ~GPIO_MBGNT;
+	GPCR = GPIO_MBGNT;
+	GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT;
+	GAFR &= ~(GPIO_MBGNT | GPIO_MBREQ);
 
 	GPDR |= (BADGE4_GPIO_SDTYP1 | BADGE4_GPIO_SDTYP0);
 

CVS: blob/src/blob memsetup-sa1110.S,1.13,1.14

[Christopher H. <ch...@us...>]

Update of /cvsroot/blob/blob/src/blob
In directory usw-pr-cvs1:/tmp/cvs-serv25657

Modified Files:
	memsetup-sa1110.S 
Log Message:
prefix register offsets with _ so as to not conflict with sa1100.h defines; add hooks for arch-specific memsetup

Index: memsetup-sa1110.S
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/memsetup-sa1110.S,v
retrieving revision 1.13
retrieving revision 1.14
diff -u -d -r1.13 -r1.14
--- memsetup-sa1110.S	19 Apr 2002 20:01:36 -0000	1.13
+++ memsetup-sa1110.S	25 Jul 2002 17:26:41 -0000	1.14
@@ -44,15 +44,43 @@
 # include <blob/config.h>
 #endif
 
+#define __ASSEMBLY__
+#include <blob/sa1100.h>
 #define BLOB_NEED_MEMCONFIG
 #include <blob/memsetup.h>
 #include <blob/arch.h>
 
-			
 .text
+.globl memsetup
+
 MEM_REG_BASE:	.long	0xa0000000
 MEM_START:	.long	MEMORY_START
 
+PWR_BASE:	.long	0x90020000
+#define _PSSR	0x04
+#define _PSPR	0x08
+#define _PPCR	0x14
+#define _POSR	0x1C
+
+/* Architecture headers can customized the memory setup behavior with
+ * the following defines:
+ *	 
+ *   ARCH_SPECIFIC_MEMSETUP	
+ *	arch does its own memort setup. must define memsetup somewhere
+ *	which should do whatever it needs to do and do a standard
+ *	assembly linkage return (mov pc, lr).
+ *
+ *   ARCH_SPECIFIC_MEMSETUP_STD
+ *      arch needs std_memsetup procedure.  ignored except when
+ *	ARCH_SPECIFIC_MEMSETUP is defined.
+ */
+	
+
+/* -------------------------------------------------- */	
+/* standard memory configuration */
+
+#if !defined(ARCH_SPECIFIC_MEMSETUP) || defined(ARCH_SPECIFIC_MEMSETUP_STD)
+	
 MEMORY_CONFIG:
 	.long	MDCNFG_VALUE		/* 0x0  MDCNFG */
 	.long	MDCAS00_VALUE		/* 0x04 MDCAS00 */
@@ -72,40 +100,32 @@
 	.long	MSC2_VALUE		/* 0x2C MSC2 */
 	.long	SMCNFG_VALUE		/* 0x30 SMCNFG */
 
-PWR_BASE:	.long	0x90020000
-#define PSSR	0x04
-#define PSPR	0x08
-#define PPCR	0x14
-#define POSR	0x1C
-
-.globl memsetup
-memsetup:
-	mov r5, lr
-
+.globl std_memsetup	
+std_memsetup:
 	/* Set up the SDRAM */
 	ldr	r0, MEM_REG_BASE
 	adr	r1, MEMORY_CONFIG
 
-	ldr	r2, [r1, #MDCNFG ]
-	str	r2, [r0, #MDCNFG ]
+	ldr	r2, [r1, #_MDCNFG ]
+	str	r2, [r0, #_MDCNFG ]
 
-	ldr	r2, [r1, #MDCAS00 ]
-	str	r2, [r0, #MDCAS00 ]
+	ldr	r2, [r1, #_MDCAS00 ]
+	str	r2, [r0, #_MDCAS00 ]
 
-	ldr	r2, [r1, #MDCAS01 ]
-	str	r2, [r0, #MDCAS01 ]
+	ldr	r2, [r1, #_MDCAS01 ]
+	str	r2, [r0, #_MDCAS01 ]
 
-	ldr	r2, [r1, #MDCAS02 ]
-	str	r2, [r0, #MDCAS02 ]
+	ldr	r2, [r1, #_MDCAS02 ]
+	str	r2, [r0, #_MDCAS02 ]
 
-	ldr	r2, [r1, #MDCAS20 ]
-	str	r2, [r0, #MDCAS20 ]
+	ldr	r2, [r1, #_MDCAS20 ]
+	str	r2, [r0, #_MDCAS20 ]
 
-	ldr	r2, [r1, #MDCAS21 ]
-	str	r2, [r0, #MDCAS21 ]
+	ldr	r2, [r1, #_MDCAS21 ]
+	str	r2, [r0, #_MDCAS21 ]
 
-	ldr	r2, [r1, #MDCAS22 ]
-	str	r2, [r0, #MDCAS22 ]
+	ldr	r2, [r1, #_MDCAS22 ]
+	str	r2, [r0, #_MDCAS22 ]
 
 	/*
 	 * Refer to sections 9.5.3.7: Reviving DRAMS from Self-Refresh Mode
@@ -123,47 +143,47 @@
 	 * NOTE: do NOT clear SSS, the kernel wants it set */
 	ldr	r1, PWR_BASE
 	mov	r2, #0x08          /* PSSR_DH */
-	str	r2, [r1, #PSSR]    /* clear DH by writing 1 to it */
+	str	r2, [r1, #_PSSR]    /* clear DH by writing 1 to it */
 
 
 #ifdef MDREFR_DONT_BELIEVE_IN_MAGIC
-	ldr	r2, [r1, #MDREFR ]
-	str	r2, [r0, #MDREFR ]
+	ldr	r2, [r1, #_MDREFR ]
+	str	r2, [r0, #_MDREFR ]
 #else
 	/* clear KxDB2 */
-	ldr r2, [ r0, #MDREFR ]
+	ldr r2, [ r0, #_MDREFR ]
 	bic r2, r2, #MDREFR_K0DB2
 	bic r2, r2, #MDREFR_K1DB2
 	bic r2, r2, #MDREFR_K2DB2
 	bic r2, r2, #0xff          /* clear TRASR and DRI */
 	bic r2, r2, #0xff00
-	str r2, [ r0, #MDREFR ]
+	str r2, [ r0, #_MDREFR ]
 
 	/* set TRASR and DRI, KxDB2 */
-	ldr r2, [ r0, #MDREFR ]
+	ldr r2, [ r0, #_MDREFR ]
 	orr r2, r2, #MDREFR_TRASR(7)
 	orr r2, r2, #MDREFR_DRI(12)
 	orr r2, r2, #MDREFR_K0DB2
 	orr r2, r2, #MDREFR_K1DB2
 	orr r2, r2, #MDREFR_K2DB2
-	str r2, [ r0, #MDREFR ]
+	str r2, [ r0, #_MDREFR ]
 
 	/* set KxRUN */
-	ldr r2, [ r0, #MDREFR ]
+	ldr r2, [ r0, #_MDREFR ]
 	orr r2, r2, #MDREFR_K0RUN
 	orr r2, r2, #MDREFR_K1RUN
 	orr r2, r2, #MDREFR_K2RUN
-	str r2, [ r0, #MDREFR ]
+	str r2, [ r0, #_MDREFR ]
 
 	/* clear SLFRSH */
-	ldr r2, [ r0, #MDREFR ]
+	ldr r2, [ r0, #_MDREFR ]
 	bic r2, r2, #MDREFR_SLFRSH
-	str r2, [ r0, #MDREFR ]
+	str r2, [ r0, #_MDREFR ]
 
 	/* toggle E1PIN (set -> clear ) */
-	ldr r2, [ r0, #MDREFR ]
+	ldr r2, [ r0, #_MDREFR ]
 	orr r2, r2, #MDREFR_E1PIN
-	str r2, [ r0, #MDREFR ]
+	str r2, [ r0, #_MDREFR ]
 #endif
 
 	/* Issue read requests to disabled bank to start refresh */
@@ -176,32 +196,45 @@
 	adr r1, MEMORY_CONFIG
 	
 	/* ENABLE SDRAM BANKS */
-	ldr	r2, [r0, #MDCNFG ]
+	ldr	r2, [r0, #_MDCNFG ]
 	orr	r2, r2, #0x00000003
 	orr	r2, r2, #0x00030000
-	str	r2, [r0, #MDCNFG]
+	str	r2, [r0, #_MDCNFG]
 
 	/* OPTIONALLY enable Autopowerup/down */
 #if 0
-	ldr r2, [ r0, #MDREFR ]
+	ldr r2, [ r0, #_MDREFR ]
 	orr r2, r2, #MDREFR_EAPD
 	orr r2, r2, #MDREFR_KAPD
-	str r2, [ r0, #MDREFR ]
+	str r2, [ r0, #_MDREFR ]
 #endif
 
-	ldr	r2, [r1, #MCS0 ]
-	str	r2, [r0, #MCS0 ]
+	ldr	r2, [r1, #_MCS0 ]
+	str	r2, [r0, #_MCS0 ]
 
-	ldr	r2, [r1, #MCS1 ]
-	str	r2, [r0, #MCS1 ]
+	ldr	r2, [r1, #_MCS1 ]
+	str	r2, [r0, #_MCS1 ]
 
-	ldr	r2, [r1, #MCS2 ]
-	str	r2, [r0, #MCS2 ]
+	ldr	r2, [r1, #_MCS2 ]
+	str	r2, [r0, #_MCS2 ]
 
-	ldr	r2, [r1, #SMCNFG ]
-	str	r2, [r0, #SMCNFG ]
+	ldr	r2, [r1, #_SMCNFG ]
+	str	r2, [r0, #_SMCNFG ]
 
-	ldr	r2, [r1, #MECR ]
-	str	r2, [r0, #MECR ]
+	ldr	r2, [r1, #_MECR ]
+	str	r2, [r0, #_MECR ]
 	
-	mov	pc, r5
+	mov	pc, lr
+#endif
+
+/* -------------------------------------------------- */	
+	
+#if !defined(ARCH_SPECIFIC_MEMSETUP)
+memsetup:
+	b	std_memsetup
+#endif
+	
+	
+/* -------------------------------------------------- */	
+	
+/* Arch specific setup */

CVS: blob/src/blob memsetup-sa1100.S,1.4,1.5

[Christopher H. <ch...@us...>]

Update of /cvsroot/blob/blob/src/blob
In directory usw-pr-cvs1:/tmp/cvs-serv25423

Modified Files:
	memsetup-sa1100.S 
Log Message:
prefix register offsets with _ so as to not conflict with sa1100.h defines

Index: memsetup-sa1100.S
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/memsetup-sa1100.S,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- memsetup-sa1100.S	4 Apr 2002 09:07:58 -0000	1.4
+++ memsetup-sa1100.S	25 Jul 2002 17:25:59 -0000	1.5
@@ -44,11 +44,11 @@
 
 MEM_BASE:	.long	0xa0000000
 MEM_START:	.long	MEMORY_START
-#define	MDCNFG	0x0
-#define MDCAS0	0x04
-#define MDCAS1	0x08
-#define MDCAS2	0x0c
-#define MCS0	0x10
+#define	_MDCNFG	0x0
+#define _MDCAS0	0x04
+#define _MDCAS1	0x08
+#define _MDCAS2	0x0c
+#define _MCS0	0x10
 
 
 
@@ -107,25 +107,25 @@
 	ldr	r0, MEM_BASE
 	
 	ldr	r1, mcs0
-	str	r1, [r0, #MCS0]
+	str	r1, [r0, #_MCS0]
 	
 	/* Set up the DRAM */
 	
 	/* MDCAS0 */
 	ldr	r1, mdcas0
-	str	r1, [r0, #MDCAS0]
+	str	r1, [r0, #_MDCAS0]
 
 	/* MDCAS1 */
 	ldr	r1, mdcas1
-	str	r1, [r0, #MDCAS1]
+	str	r1, [r0, #_MDCAS1]
 
 	/* MDCAS2 */
 	ldr	r1, mdcas2
-	str	r1, [r0, #MDCAS2]
+	str	r1, [r0, #_MDCAS2]
 
 	/* MDCNFG */
 	ldr	r1, mdcnfg
-	str	r1, [r0, #MDCNFG]
+	str	r1, [r0, #_MDCNFG]
 
 	/* Issue read requests to disabled bank to start refresh */
 	/* this is required by the Micron memory on a TuxScreen */

CVS: blob/src/blob start-sa11x0.S,1.3,1.4

[Christopher H. <ch...@us...>]

Update of /cvsroot/blob/blob/src/blob
In directory usw-pr-cvs1:/tmp/cvs-serv25113

Modified Files:
	start-sa11x0.S 
Log Message:
prefix register offsets with _ so as to not conflict with sa1100.h defines

Index: start-sa11x0.S
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/start-sa11x0.S,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- start-sa11x0.S	19 Apr 2002 20:01:36 -0000	1.3
+++ start-sa11x0.S	25 Jul 2002 17:25:20 -0000	1.4
@@ -44,16 +44,16 @@
 /* some defines to make life easier */
 /* Register addresses can be found in [1] Appendix A */
 IC_BASE:        .word   0x90050000
-#define ICMR    0x04
+#define _ICMR    0x04
 	
 PWR_BASE:	.word	0x90020000
-#define PSSR	0x04
-#define PSPR	0x08
-#define PPCR	0x14
-#define POSR	0x1C
+#define _PSSR	0x04
+#define _PSPR	0x08
+#define _PPCR	0x14
+#define _POSR	0x1C
 	
 RST_BASE:	.word	0x90030000
-#define RCSR	0x04
+#define _RCSR	0x04
 
 
 
@@ -76,16 +76,16 @@
 	/* First, mask **ALL** interrupts */
 	ldr	r0, IC_BASE
 	mov	r1, #0x00
-	str	r1, [r0, #ICMR]
+	str	r1, [r0, #_ICMR]
 
 	/* switch CPU to correct speed */
 	ldr	r0, PWR_BASE
 	ldr	r1, cpuspeed
-	str	r1, [r0, #PPCR]
+	str	r1, [r0, #_PPCR]
 
 	/* check if this is a wake-up from sleep */
 	ldr	r0, RST_BASE
-	ldr	r1, [r0, #RCSR]
+	ldr	r1, [r0, #_RCSR]
 	and	r1, r1, #0x0f
 	tst	r1, #0x08	/* check the Sleep Mode Reset bit */
 	beq	real_reset	/* no, continue booting */
@@ -93,14 +93,14 @@
 	/* Wait for the oscillator to stabilize */
 	ldr	r0, PWR_BASE
 wait_for_OOK:
-	ldr	r1, [r0, #POSR]
+	ldr	r1, [r0, #_POSR]
 	tst	r1, #1		/* test Oscillator OK bit */
 	beq	wait_for_OOK
 
 	/* yes, a wake-up. clear RCSR by writing a 1 (see 9.6.2.1 from [1]) */
 	ldr	r0, RST_BASE
 	mov	r1, #0x08
-	str	r1, [r0, #RCSR]	;
+	str	r1, [r0, #_RCSR]	;
 
 	/* setup memory */
 	bl	memsetup
@@ -108,14 +108,14 @@
 	/* handle Power Manager Sleep Status Register (PSSR)
 	 * see 9.5.7.5 from [1]*/
 	ldr	r0, PWR_BASE
-	ldr r1, [r0, #PSSR]
+	ldr r1, [r0, #_PSSR]
 	/* clear PH bit, bring periperal pins out from sleep state */
 	orr r1, r1, #0x10
-	str r1, [r0, #PSSR]
+	str r1, [r0, #_PSSR]
 	
 	/* get the value from the PSPR and jump to it */
 	ldr	r0, PWR_BASE
-	ldr	r1, [r0, #PSPR]
+	ldr	r1, [r0, #_PSPR]
 	mov	pc, r1
 
 	

CVS: blob/src/blob ledasm.S,1.3,1.4

[Christopher H. <ch...@us...>]

Update of /cvsroot/blob/blob/src/blob
In directory usw-pr-cvs1:/tmp/cvs-serv24870

Modified Files:
	ledasm.S 
Log Message:
prefix register offsets with _ so as to not conflict with sa1100.h defines

Index: ledasm.S
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/ledasm.S,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- ledasm.S	28 Oct 2001 20:29:05 -0000	1.3
+++ ledasm.S	25 Jul 2002 17:24:36 -0000	1.4
@@ -33,16 +33,15 @@
 #endif
 
 #include <blob/arch.h>
-
-
+#include <blob/sa1100.h>
 
 .text
 
 LED:		.long LED_GPIO
 GPIO_BASE:	.long 0x90040000
-#define	GPDR	0x00000004
-#define GPSR	0x00000008
-#define GPCR	0x0000000c
+#define	_GPDR	0x00000004
+#define _GPSR	0x00000008
+#define _GPCR	0x0000000c
 
 
 
@@ -54,8 +53,8 @@
 ledinit:
 	ldr	r0, GPIO_BASE
 	ldr	r1, LED
-	str	r1, [r0, #GPDR]		/* LED GPIO is output */
-	str	r1, [r0, #GPSR]		/* turn LED on */
+	str	r1, [r0, #_GPDR]		/* LED GPIO is output */
+	str	r1, [r0, #_GPSR]		/* turn LED on */
 	mov	pc, lr
 
 
@@ -66,7 +65,7 @@
 led_on:
 	ldr	r0, GPIO_BASE
 	ldr	r1, LED
-	str	r1, [r0, #GPSR]
+	str	r1, [r0, #_GPSR]
 	mov	pc, lr
 
 
@@ -77,7 +76,7 @@
 led_off:
 	ldr	r0, GPIO_BASE
 	ldr	r1, LED
-	str	r1, [r0, #GPCR]
+	str	r1, [r0, #_GPCR]
 	mov	pc, lr
 
 

Blob port to xscale processors

[Jeff S. <je...@ac...>]

I've finally got off my rear and started the port to the PXA250 processor=
=2E =20
Anyone else working on this, or have plans to?  I know of at least one li=
st=20
member that has an Accelent PXA IDP besides myself...
--=20
  Jeff Sutherland, Accelent Systems, Inc.   <http://www.accelent.com>
  -  +  -  +  -  +  -  +  -  +  -  +  -  +  -  +  -  +  -  +  -  +  - =20
Kodachrome: After nearly 70 years there's still no better way to
preserve an image.

CVS: blob/include/blob/arch system3.h,1.17,1.18

[Stefan E. <se...@us...>]

Update of /cvsroot/blob/blob/include/blob/arch
In directory usw-pr-cvs1:/tmp/cvs-serv22593

Modified Files:
	system3.h 
Log Message:
- split up cramfs.img in root and data filesystems


Index: system3.h
===================================================================
RCS file: /cvsroot/blob/blob/include/blob/arch/system3.h,v
retrieving revision 1.17
retrieving revision 1.18
diff -u -d -r1.17 -r1.18
--- system3.h	13 May 2002 09:38:59 -0000	1.17
+++ system3.h	25 Jul 2002 14:21:42 -0000	1.18
@@ -30,8 +30,8 @@
 #undef	CPU_SPEED_133
 
 /* SYSTEM3 with 64 MB SDRAM, all on bank0 */
-//#undef CONFIG_SYSTEM3_REV0802
-#define CONFIG_SYSTEM3_REV0802
+#undef CONFIG_SYSTEM3_REV0802
+//#define CONFIG_SYSTEM3_REV0802
 
 /* boot CPU speed */
 #ifdef CPU_SPEED_133
@@ -71,8 +71,10 @@
 #define LOAD_RAMDISK		1 /* load ramdisk into ram */
 #define RAMDISK_FLASH_BASE	(0x00180000)
 #define RAMDISK_FLASH_LEN	(1536 * 1024)
-#define CRAMFS_FLASH_BASE	(0x00300000)
-#define CRAMFS_FLASH_LEN	(13312 * 1024)
+#define ROOTFS_FLASH_BASE	(0x00300000)
+#define ROOTFS_FLASH_LEN	(0x00600000) /* 6M */
+#define DATAFS_FLASH_BASE	(0x00900000)
+#define DATAFS_FLASH_LEN	(0x00700000) /* 7M */
 
 /* system3 RAM pool for up/downloading */
 #if !defined(CONFIG_SYSTEM3_REV0802)
@@ -91,6 +93,13 @@
 /* the size (in kbytes) to which the compressed ramdisk expands */
 #define RAMDISK_SIZE		(8 * 1024)
 
+/* let SDRAM run at FULL memclk speed */
+#undef MDREFR_MEMCLK_FULLSPEED_0
+#undef MDREFR_MEMCLK_FULLSPEED_1
+#undef MDREFR_MEMCLK_FULLSPEED_2
+//#define MDREFR_MEMCLK_FULLSPEED_0
+//#define MDREFR_MEMCLK_FULLSPEED_1
+//#define MDREFR_MEMCLK_FULLSPEED_2
 
 /* Memory configuration */
 #ifdef BLOB_NEED_MEMCONFIG
@@ -105,7 +114,6 @@
 #define MSC0_VALUE_100_120	MSC_RT_ROMFLASH | MSC_RBW32 | MSC_RDF(13) | MSC_RDN(3) | MSC_RRR(2)
 #define MSC0_VALUE_100_100	MSC_RT_ROMFLASH | MSC_RBW32 | MSC_RDF(11) | MSC_RDN(3) | MSC_RRR(2)
 #define MSC1_VALUE_100		MSC_RT_ROMFLASH | MSC_RBW16 | MSC_RDF(5)  | MSC_RDN(1) | MSC_RRR(1)| ((MSC_RT_VARLAT_345 | MSC_RBW16 | MSC_RDF(30)  | MSC_RDN(30) | MSC_RRR(7))<<16)
-//#define MSC2_VALUE_100	MSC_RT_VARLAT_345 | MSC_RBW32 | MSC_RDF(9)  | MSC_RDN(2) | MSC_RRR(1)
 #define MSC2_VALUE_100		MSC_RT_VARLAT_345 | MSC_RBW32 | MSC_RDF(13)  | MSC_RDN(6) | MSC_RRR(3)
 #define MECR_VALUE_100		MECR_BSIO0(0x1f) | MECR_BSA0(0x1f) | MECR_BSM0(0x1f) | MECR_BSIO1(0x1f) | MECR_BSA1(0x1f) | MECR_BSM1(0x1f)
 

CVS: blob/src/blob system3.c,1.22,1.23

[Stefan E. <se...@us...>]

Update of /cvsroot/blob/blob/src/blob
In directory usw-pr-cvs1:/tmp/cvs-serv22289

Modified Files:
	system3.c 
Log Message:
- split up cramfs.img in root and data filesystems


Index: system3.c
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/system3.c,v
retrieving revision 1.22
retrieving revision 1.23
diff -u -d -r1.22 -r1.23
--- system3.c	25 Jul 2002 14:06:12 -0000	1.22
+++ system3.c	25 Jul 2002 14:21:02 -0000	1.23
@@ -130,8 +130,9 @@
 0x00040000 CONFIG	256k
 0x00080000 KERNEL	1024k
 0x00180000 INITRD	1536k
-0x00300000 CRAMFS	13312k
-0x01000000
+0x00300000 ROOT		6M
+0x00900000 DATA		7M
+0x01000000 total	16M
 
 Note:
 	- system3 partitions are named like the files they're flashed
@@ -191,9 +192,18 @@
 		/* root (cramfs) */
 		magic:		BLOB_PART_VALID_MAGIC,
 		next:		sizeof(blob_partition_t),
-		offset:		CRAMFS_FLASH_BASE,
-		size:		CRAMFS_FLASH_LEN,
-		name:		"cramfs.img",
+		offset:		ROOTFS_FLASH_BASE,
+		size:		ROOTFS_FLASH_LEN,
+		name:		"root.img",
+		flags:		BLOB_PART_FLAG_CRAMFS,
+	},
+	{
+		/* data (cramfs) */
+		magic:		BLOB_PART_VALID_MAGIC,
+		next:		sizeof(blob_partition_t),
+		offset:		DATAFS_FLASH_BASE,
+		size:		DATAFS_FLASH_LEN,
+		name:		"data.img",
 		flags:		BLOB_PART_FLAG_CRAMFS,
 	},
 	{
@@ -453,7 +463,7 @@
 {
 	int ret;
 	char *update_files[] = { "blob", "config.tar", "zImage", "initrd.gz",
-		"cramfs.img", NULL };
+		"root.img", "data.img", NULL };
 	char *image = NULL;
 	int i=0;
 	char *source = "CF";

CVS: blob/src/lib tar.c,1.4,1.5

[Stefan E. <se...@us...>]

Update of /cvsroot/blob/blob/src/lib
In directory usw-pr-cvs1:/tmp/cvs-serv17161

Modified Files:
	tar.c 
Log Message:
- allow GNU tar headers and POSIX headers


Index: tar.c
===================================================================
RCS file: /cvsroot/blob/blob/src/lib/tar.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- tar.c	3 May 2002 09:59:16 -0000	1.4
+++ tar.c	25 Jul 2002 14:08:00 -0000	1.5
@@ -151,6 +151,7 @@
 		return -EINVAL;
 
 	name = (char *)conf;
+	DBG( 5, "%s: name=%s\n", __FUNCTION__, name );
 
 	/* init new archive struct */
 	ret = tar_init( arch, child );
@@ -434,7 +435,7 @@
 		return -EINVAL;
 
 	/* check magic */
-	ret = strncmp( hdr->magic, TMAGIC, TMAGLEN );
+	ret = strncmp( hdr->magic, TMAGIC, 5 ); // "ustar"
 	if ( ret != 0 )
 		return -EINVAL;
 

CVS: blob/src/blob system3.c,1.21,1.22

[Stefan E. <se...@us...>]

Update of /cvsroot/blob/blob/src/blob
In directory usw-pr-cvs1:/tmp/cvs-serv16555

Modified Files:
	system3.c 
Log Message:
- system3 GPIO settings


Index: system3.c
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/system3.c,v
retrieving revision 1.21
retrieving revision 1.22
diff -u -d -r1.21 -r1.22
--- system3.c	13 May 2002 09:36:22 -0000	1.21
+++ system3.c	25 Jul 2002 14:06:12 -0000	1.22
@@ -2,7 +2,7 @@
  * system3.c: PT System3 specific stuff
  *
  * Copyright (C) 2001  Erik Mouw (J.A...@it...)
- * Copyright (C) 2001  Stefan Eletzhofer 
+ * Copyright (C) 2001,2002  Stefan Eletzhofer 
  *                               (ste...@ww...)
  *
  * This program is free software; you can redistribute it and/or modify
@@ -231,6 +231,11 @@
 	MEM(SYSTEM3_CTRL_1) = 0x00;
 	MEM(SYSTEM3_CTRL_2) = 0x00;
 
+	/* initialize GPIO states */
+	GPDR = 0x0f35a7fc;
+	GPSR |= GPIO_GPIO15 | GPIO_GPIO20; /* 15: core fast, 20: SCL */
+	GPCR |= 0x070527fc;
+
 	/* activate SYSCLCK for keyboard controller */
 	RST( MEM(TUCR), 31 );
 	GAFR |= GPIO_32_768kHz;
@@ -395,7 +400,6 @@
 int pcmcia_init()
 {
 	printf( "PT Digital Board PCMCIA init\n" );
-	//sa1111_init();
 	return 0;
 }
 #endif
@@ -430,7 +434,7 @@
 		return -EINVAL;
 	}
 
-#if 1
+#if !defined(SYSUPD_DUMMY_COPY)
 	/* flash tha image, man! */
 	ret = io_copy( "BLOB_PART", "TAR", 0 );
 	if ( ret ) {
@@ -850,11 +854,13 @@
  * manually reference flash and download commands until they
  * are in libblob.
  */
+#if 0
 extern int cf_test_module( int argc, char *argv[] );
 extern char cf_help[];
 __commandlist(cf_test_module, "cftest", cf_help);
+#endif
 
-#if 0
+#if 1
 extern int fwrite_cmd(int argc, char *argv[]);
 extern char fwrite_help[];
 __commandlist(fwrite_cmd, "fwrite", fwrite_help);

CVS: blob/src/blob badge4.c,1.8,1.9

[Christopher H. <ch...@us...>]

Update of /cvsroot/blob/blob/src/blob
In directory usw-pr-cvs1:/tmp/cvs-serv16484/src/blob

Modified Files:
	badge4.c 
Log Message:
fix memory size computation; small bits of cleanup

Index: badge4.c
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/badge4.c,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -d -r1.8 -r1.9
--- badge4.c	2 May 2002 01:45:39 -0000	1.8
+++ badge4.c	23 Jul 2002 20:06:44 -0000	1.9
@@ -77,16 +77,24 @@
 
 static void badge4_select_drivers(void)
 {
-	/* select serial driver */
 	serial_driver = &sa11x0_serial_driver;
 
 	flash_descriptors = badge4_flash_descriptors;
 	flash_driver = &intel16_flash_driver;
 }
-
 __initlist(badge4_select_drivers, INIT_LEVEL_DRIVER_SELECTION);
 
 
+static void badge4_banner(void)
+{
+	printf("\n\n\n" BOARD_NAME "\n"
+	       "Blob port by Christopher Hoover <ch...@hp...>.\n"
+	       "($Id$, " __DATE__ ")\n"
+	       "\n");
+}
+__initlist(badge4_banner, INIT_LEVEL_INITIAL_HARDWARE + 1);
+
+
 static void badge4_init_sa1111(void)
 {
 	/*
@@ -126,11 +134,10 @@
 {
 	int i, size;
 	int typ0, typ1;
-	int memory_type, row_bits, col_bits, row_density;
+	int memory_type, row_bits, col_bits, module_rows, row_density;
 	u8 spd[128];
 
-	printf("\n\n\n" BOARD_NAME "\n"
-	       "Blob port by Christopher Hoover <ch...@hp...>\n\n");
+	GPDR |= (BADGE4_GPIO_SDTYP1 | BADGE4_GPIO_SDTYP0);
 
 	/* Intialize the I2C bus and driver. */
 	i2c_init(&badge4_i2c_bus);
@@ -157,6 +164,7 @@
 
 	row_bits = spd[SPD_ROW_BITS];
 	col_bits = spd[SPD_COL_BITS];
+	module_rows = spd[SPD_MODULE_ROWS];
 	row_density = spd[SPD_ROW_DENSITY];
 
 	/* calculate the size: bit 0 is 4M, bit 1 is 8M, etc. */
@@ -164,9 +172,10 @@
 	for (i = 0; i < 8; i++)
 		if (row_density & (1<<i))
 			size += (4<<i);
+	size *= module_rows;
 
-	printf("SDRAM: %d Mbytes (row bits=%d, col bits=%d)\n", 
-	       size, row_bits, col_bits);
+	printf("SDRAM: %d Mbytes (rows=%d, row bits=%d, col bits=%d)\n", 
+	       size, module_rows, row_bits, col_bits);
 
 	/*
 	 * Here's what the CPLD expects
@@ -185,21 +194,20 @@
 	} else if (row_bits == 13 && col_bits == 9) {
 		typ1 = 1; typ0 = 0;
 	} else {
-		printf("SDRAM: unexpected SDRAM geometry\n");
+		printf("SDRAM: unexpected geometry\n");
 		goto fail;
 	}
 
  set:
-	printf("SDRAM: setting type typ1=%d, typ0=%d\n", typ1, typ0);
-	GPDR |= (BADGE4_GPIO_SDTYP0 | BADGE4_GPIO_SDTYP1);
-	if (typ0)
-		GPSR = BADGE4_GPIO_SDTYP0;
-	else
-		GPCR = BADGE4_GPIO_SDTYP0;
+	printf("SDRAM: setting CPLD typ1=%d, typ0=%d\n", typ1, typ0);
 	if (typ1)
 		GPSR = BADGE4_GPIO_SDTYP1;
 	else
 		GPCR = BADGE4_GPIO_SDTYP1;
+	if (typ0)
+		GPSR = BADGE4_GPIO_SDTYP0;
+	else
+		GPCR = BADGE4_GPIO_SDTYP0;
 
 	return;
 
@@ -209,9 +217,10 @@
 	goto set;
 }
 
-static void badge4_init_hardware(void)
+static void badge4_init_hardware2(void)
 {
 	badge4_init_sa1111();
 	badge4_setup_sdram();
 }
-__initlist(badge4_init_hardware, INIT_LEVEL_INITIAL_HARDWARE + 1);
+__initlist(badge4_init_hardware2, INIT_LEVEL_INITIAL_HARDWARE + 2);
+

CVS: blob/src/blob start.S,1.8,1.9

[Erik M. <er...@us...>]

Update of /cvsroot/blob/blob/src/blob
In directory usw-pr-cvs1:/tmp/cvs-serv15961

Modified Files:
	start.S 
Log Message:
A bit of IRC log to explain:
16:59 <erikm> blob prints something before it even starts the mem test loop
17:00 <erikm> if it doesn't, it's time for LED/scope debugging
17:04 <xhomie> I Try to make LED debugging :-). I can turn the LED on in
               mem_test_loop: but not in relocate:. So I think the Problem
	       is in mem_test_loop.
17:04 <erikm> oh, it is still stuck in the first stage loader?
17:05 <xhomie> It looks so.
17:06 * erikm spots a bug in mem_test_loop
17:07 <erikm>         moveq   pc, lr          /* oops, something went wrong :( */
17:07 <erikm> that's obviously wrong
17:08 <erikm> mem_test_loop isn't called from another function, so lr still
              contains the value of the instruction just above it
17:08 <erikm> in that case we'll get a tight loop containing only two
              instructions:
17:08 <erikm>         teq     r0, #1
17:08 <erikm>         moveq   pc, lr          /* oops, something went wrong :( */
17:11 * erikm looks for a good idea to fix it
17:11 <erikm> hmmm'
17:11 <erikm> need to rewrite start.S a bit
17:11 <erikm> hmmm

This is a temporary fix, I need to make something better, but I need to
rewrite start.S anyway (I also want to be able to do IRQ and FIQ).
Note: this patch is not tested, but should be obviously OK. xhomie should
be able to put LED blink code in endless_loop.


Index: start.S
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/start.S,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -d -r1.8 -r1.9
--- start.S	18 Jan 2002 22:32:00 -0000	1.8
+++ start.S	19 Jul 2002 15:20:03 -0000	1.9
@@ -72,7 +72,7 @@
 	mov	r0, r5
 	bl	testram
 	teq	r0, #1
-	moveq	pc, lr		/* oops, something went wrong :( */
+	beq	endless_loop	/* oops, something went wrong :( */
 
 	add	r5, r5, r7
 	subs	r6, r6, r7
@@ -101,3 +101,11 @@
 	/* blob is copied to ram, so jump to it */
 	ldr	r0, BLOB_START
 	mov	pc, r0
+
+endless_loop:
+	/* either the second stage loader returned, or we got here from
+	 * mem_test_loop. both is bad, and we really want to toggle a
+	 * GPIO line or so. for the time being we just do an endless
+	 * loop. FIXME! -- erik 
+	 */
+	b	endless_loop

CVS: blob/include/blob/arch idr.h,1.12,1.13

[Tim R. <tim...@us...>]

Update of /cvsroot/blob/blob/include/blob/arch
In directory usw-pr-cvs1:/tmp/cvs-serv6058/include/blob/arch

Modified Files:
	idr.h 
Log Message:
should be 206, but only 191 seems to work

Index: idr.h
===================================================================
RCS file: /cvsroot/blob/blob/include/blob/arch/idr.h,v
retrieving revision 1.12
retrieving revision 1.13
diff -u -d -r1.12 -r1.13
--- idr.h	6 Jul 2002 08:28:31 -0000	1.12
+++ idr.h	18 Jul 2002 08:58:45 -0000	1.13
@@ -25,7 +25,8 @@
 #define BLOB_ARCH_IDR_H
 
 /* boot CPU speed */
-#define CPU_SPEED		(CPU_CORE_SPEED_206mhz)
+//#define CPU_SPEED		(CPU_CORE_SPEED_206mhz)
+#define CPU_SPEED		(CPU_CORE_SPEED_191mhz)
 
 /* serial port */
 #define USE_SERIAL3
@@ -71,22 +72,27 @@
 /* the size (in kbytes) to which the compressed ramdisk expands */
 #define RAMDISK_SIZE		(8 * 1024)
 
+/* RAS0 ram */
+/* CS0 flash */
+/* CS3 Xilinx */
+/* CS4 sa1111 */
+/* CS5 lucent modem */
 /* Memory configuration */
 #ifdef BLOB_NEED_MEMCONFIG
 #warning "use defines from memsetup.h for better readability"
-#	define MDCNFG_VALUE	0x72577257		/* 0x0 MDCNFG 14 rows */
-#	define MDCAS00_VALUE	0x55555557		/* 0x04 MDCAS00 */
+#	define MDCNFG_VALUE	0xb257b257		/* 0x0 MDCNFG 14 rows */
+#	define MDCAS00_VALUE	0x5555557F		/* 0x04 MDCAS00 */
 #	define MDCAS01_VALUE	0x55555555		/* 0x08 MDCAS01 */
 #	define MDCAS02_VALUE	0x55555555		/* 0x0c MDCAS02 */
-#	define MSC0_VALUE	0x00004374		/* 0x10 MCS0 */
-#	define MSC1_VALUE	0x22212419		/* 0x14 MCS1 */
+#	define MSC0_VALUE	0x00004f74		/* 0x10 MCS0 */
+#	define MSC1_VALUE	0x4f714f71		/* 0x14 MCS1 */
 #	define MECR_VALUE	0x00000000		/* 0x18 MECR */
 #	define MDREFR_VALUE	DO_NOT_USE_THIS_VALUE__GETS_AUTOMAGICALLY_COMPUTED
-#	define MDCAS20_VALUE	0x55555557		/* 0x20 MDCAS20 */
+#	define MDCAS20_VALUE	0x5555557F		/* 0x20 MDCAS20 */
 #	define MDCAS21_VALUE	0x55555555		/* 0x24 MDCAS21 */
 #	define MDCAS22_VALUE	0x55555555		/* 0x28 MDCAS22 */
-#	define MSC2_VALUE	0x44396669		/* 0x2C MCS2 */
-#	define SMCNFG_VALUE	0xA040A040		/* 0x30 SMCNFG */
+#	define MSC2_VALUE	0x66694f71		/* 0x2C MCS2 */
+#	define SMCNFG_VALUE	0x00000000		/* 0x30 SMCNFG */
 #endif
 
 #endif

CVS: blob/include/blob/arch badge4.h,1.7,1.8

[Christopher H. <ch...@us...>]

Update of /cvsroot/blob/blob/include/blob/arch
In directory usw-pr-cvs1:/tmp/cvs-serv3555/include/blob/arch

Modified Files:
	badge4.h 
Log Message:
Some BadgePAD 4's (mine!) have an LED on GPIO 9.


Index: badge4.h
===================================================================
RCS file: /cvsroot/blob/blob/include/blob/arch/badge4.h,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -d -r1.7 -r1.8
--- badge4.h	27 Apr 2002 00:55:04 -0000	1.7
+++ badge4.h	13 Jul 2002 00:44:34 -0000	1.8
@@ -51,7 +51,7 @@
 #define TERMINAL_SPEED baud_115200
 
 /* GPIO for the LED */
-#define LED_GPIO		(0x00000000) /* No LED */
+#define LED_GPIO		(0x00000001<<9) /* GPIO 9 */
 
 #define SA1111_BASE		BADGE4_SA1111_BASE
 

CVS: blob/include/blob/arch idr.h,1.11,1.12

[Tim R. <tim...@us...>]

Update of /cvsroot/blob/blob/include/blob/arch
In directory usw-pr-cvs1:/tmp/cvs-serv21607/include/blob/arch

Modified Files:
	idr.h 
Log Message:
speed up cpu and flash

Index: idr.h
===================================================================
RCS file: /cvsroot/blob/blob/include/blob/arch/idr.h,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -d -r1.11 -r1.12
--- idr.h	30 Apr 2002 23:29:45 -0000	1.11
+++ idr.h	6 Jul 2002 08:28:31 -0000	1.12
@@ -25,7 +25,7 @@
 #define BLOB_ARCH_IDR_H
 
 /* boot CPU speed */
-#define CPU_SPEED		(CPU_CORE_SPEED_132mhz)
+#define CPU_SPEED		(CPU_CORE_SPEED_206mhz)
 
 /* serial port */
 #define USE_SERIAL3
@@ -74,12 +74,11 @@
 /* Memory configuration */
 #ifdef BLOB_NEED_MEMCONFIG
 #warning "use defines from memsetup.h for better readability"
-/* #	define MDCNFG_VALUE	0x72347234 */	/* 0x0  MDCNFG  12 rows*/ 
-#	define MDCNFG_VALUE	0x72547254		/* 0x0  MDCNFG 14 rows */
+#	define MDCNFG_VALUE	0x72577257		/* 0x0 MDCNFG 14 rows */
 #	define MDCAS00_VALUE	0x55555557		/* 0x04 MDCAS00 */
 #	define MDCAS01_VALUE	0x55555555		/* 0x08 MDCAS01 */
 #	define MDCAS02_VALUE	0x55555555		/* 0x0c MDCAS02 */
-#	define MSC0_VALUE	0x00004B94		/* 0x10 MCS0 */
+#	define MSC0_VALUE	0x00004374		/* 0x10 MCS0 */
 #	define MSC1_VALUE	0x22212419		/* 0x14 MCS1 */
 #	define MECR_VALUE	0x00000000		/* 0x18 MECR */
 #	define MDREFR_VALUE	DO_NOT_USE_THIS_VALUE__GETS_AUTOMAGICALLY_COMPUTED

CVS: blob .cvsignore,1.3,1.4

[Tim R. <tim...@us...>]

Update of /cvsroot/blob/blob
In directory usw-pr-cvs1:/tmp/cvs-serv21559

Modified Files:
	.cvsignore 
Log Message:
stop bugging be about diffs

Index: .cvsignore
===================================================================
RCS file: /cvsroot/blob/blob/.cvsignore,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- .cvsignore	27 Apr 2002 00:55:04 -0000	1.3
+++ .cvsignore	6 Jul 2002 08:28:11 -0000	1.4
@@ -5,4 +5,5 @@
 config.status
 Makefile.in
 Makefile
+*.diff
 junk

CVS: blob/src/blob amd32.c,1.5,1.6

[Russ D. <ru...@us...>]

Update of /cvsroot/blob/blob/src/blob
In directory usw-pr-cvs1:/tmp/cvs-serv27030

Modified Files:
	amd32.c 
Log Message:
amd32 flash rewrite

Index: amd32.c
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/amd32.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- amd32.c	29 Apr 2002 21:32:43 -0000	1.5
+++ amd32.c	19 Jun 2002 04:41:49 -0000	1.6
@@ -18,6 +18,8 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  *
+ * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/21358.pdf
+ *
  */
 
 #ident "$Id$"
@@ -36,6 +38,9 @@
 #define READ_ARRAY		0x00F000F0
 #define UNLOCK1			0x00AA00AA
 #define UNLOCK2			0x00550055
+#define CONFIG_QUERY		0x00900090
+#define EXIT_UNLOCK1		0x00900090
+#define EXIT_UNLOCK2		0x00000000
 #define ERASE_SETUP		0x00800080
 #define ERASE_CONFIRM		0x00300030
 #define PGM_SETUP		0x00A000A0
@@ -43,21 +48,70 @@
 #define FLASH_ADDR1		(0x00000555 << 2)
 #define FLASH_ADDR2		(0x000002AA << 2)
 #define ERASE_DONE		0x00800080
+#define TOGGLE_BIT		0x00400040
 #define RDY_MASK		0x00800080
 #define STATUS_PGM_ERR		0x00200020
 #define STATUS_ERASE_ERR	0x00000001
 
-#define READY 1
-#define ERR   2
+#define READY 		1
+#define LAST_CHANCE 	2
+#define LAST_CHANCE2	3
+#define ERR		4
 
 
+static void flash_read_array_amd32(void)
+{
+	*(u32 *)FLASH_ADDR1 = data_to_flash(READ_ARRAY);
+	barrier();
+}
 
+/* NOT! for amd16.c, this examines one chip of the two chip interleave */
+static int get_status_amd16(u32 result, u32 last, int chip)
+{
+	if (chip == LAST_CHANCE)
+		chip = LAST_CHANCE2;
+	else if (!(result ^ last)) /* didn't toggle */
+		chip = READY;
+	else if (chip == LAST_CHANCE2)
+		chip = ERR;
+	else if (result & STATUS_PGM_ERR)
+		chip = LAST_CHANCE;
+	return chip;
+}
 
-static int flash_erase_amd32(u32 *addr)
+static int get_status_amd32(u32 *addr)
 {
-	u32 result;
+	u32 result, last;
 	int chip1, chip2;
 
+	chip1 = chip2 = 0;
+
+	last = data_from_flash(*addr);
+	barrier();
+
+	do {
+		result = data_from_flash(*addr);
+		barrier();
+
+		if ((chip1 != ERR && chip1 != READY))
+			chip1 = get_status_amd16(result & 0xFFFF, last & 0xFFFF, chip1);
+
+		if ((chip2 != ERR && chip2 != READY))
+			chip2 = get_status_amd16(result >> 16, last >> 16, chip2);
+	
+		last = result;
+
+	} while ((chip1 != ERR && chip1 != READY) || (chip2 != ERR && chip2 != READY));
+
+	if (chip1 == ERR || chip2 == ERR) return -1;
+	
+	return 0;
+
+}
+
+
+static int flash_erase_amd32(u32 *addr)
+{
 	/* prepare for erase */
 	*(u32 *)FLASH_ADDR1 = data_to_flash(UNLOCK1);
 	barrier();
@@ -81,32 +135,18 @@
 
 	/* Russ, why don't you do this like the LART does? Just check
          * the status of chips with a single compare. -- Erik */
-	chip1 = chip2 = 0;
-
-	do {
-		result = data_from_flash(*addr);
-		barrier();
-
-		if (!chip1 && (result & 0xFFFF) & ERASE_DONE)
-			chip1 = READY;
 
-		if (!chip1 && (result & 0xFFFF) & STATUS_PGM_ERR) 
-			chip1 = ERR;
-
-		if (!chip2 && (result >> 16) & ERASE_DONE)
-			chip2 = READY;
+	/* Maybe this restructuring will amke it more clear, when the flash
+	 * is done erasing, it will return 0xFFFF on read, which contains the
+	 * status pgm err bit. So an error condition occurs if the status pgm
+	 * bit is set, but the erase done bit is not. OK, switch this over
+	 * to detecting bit toggles. --Russ */
 
-		if (!chip2 && (result >> 16) & STATUS_PGM_ERR)
-			chip2 = ERR;
-		
-	} while(!chip1 || !chip2);
-	
-	/* put flash back into Read Array mode */
-	*(u32 *)FLASH_ADDR1 = data_to_flash(READ_ARRAY);
-	barrier();
-	
-	if (chip1 == ERR || chip2 == ERR)
+	if (get_status_amd32(addr) < 0) {
+		/* put flash back into Read Array mode */
+		flash_read_array_amd32();
 		return -EFLASHERASE;
+	}
 
 	return 0;
 }
@@ -116,66 +156,22 @@
 
 static int flash_write_amd32(u32 *dst, const u32* src)
 {
-	u32 result;
-	int chip1, chip2;
 
 	*(u32 *)FLASH_ADDR1 = data_to_flash(UNLOCK1);
 	barrier();
 	*(u32 *)FLASH_ADDR2 = data_to_flash(UNLOCK2);
 	barrier();
-	*(u32 *)FLASH_ADDR1 = data_to_flash(UNLOCK_BYPASS);
+	*(u32 *)FLASH_ADDR1 = data_to_flash(PGM_SETUP);
 	barrier();
 
-	*dst = data_to_flash(PGM_SETUP);
-	barrier();
 	*dst = *src;
 	barrier();
 	
-	/* This is a pretty similar situation to the erasing status below
-	 * Bit 7 is ~(data bit 7) until the flash is complete. If bit 5
-	 * gets set before this happens, there is an error, but this could
-	 * happen near the clock edge, and bit 5 could be the actual data 
-	 * before bit 7 changes, so we have to read again. -- Russ
-	 */ 
-
-	chip1 = chip2 = 0;
-	do {
-		result = data_from_flash(*dst);
+	if (get_status_amd32(dst) < 0 || *dst != *src) {
 		barrier();
-
-		if (!chip1 && ((result & 0x80) == (*src & 0x80))) 
-			chip1 = READY;
-
-		if (!chip1 && ((result & 0xFFFF) & STATUS_PGM_ERR)) {
-			result = data_from_flash(*dst);
-			barrier();
-
-			if ((result & 0x80) == (*src & 0x80))
-				chip1 = READY;
-			else 
-				chip1 = ERR;
-		}
-
-		if (!chip2 && ((result & (0x80 << 16)) == (*src & (0x80 << 16))))
-			chip2 = READY;
-
-		if (!chip2 && ((result >> 16) & STATUS_PGM_ERR)) {
-			result = data_from_flash(*dst);
-			barrier();
-
-			if ((result & (0x80 << 16)) == (*src & (0x80 << 16)))
-				chip2 = READY;
-			else 
-				chip2 = ERR;
-		}
-
-	} while (!chip1 || !chip2);
-		
-	*(u32 *)FLASH_ADDR1 = data_to_flash(READ_ARRAY);
-	barrier();
-
-	if (chip1 == ERR || chip2 == ERR || *dst != *src)
+		flash_read_array_amd32();	
 		return -EFLASHPGM;
+	}
 
 	return 0;
 }
@@ -203,8 +199,18 @@
 
 static int flash_query_block_lock_amd32(u32 *blockStart)
 {
-	/* FIXME: this function should be fleshed out -- Erik */
-	return 0;
+	int result;
+	*(u32 *)FLASH_ADDR1 = data_to_flash(UNLOCK1);
+	barrier();
+	*(u32 *)FLASH_ADDR2 = data_to_flash(UNLOCK2);
+	barrier();
+	*(u32 *)FLASH_ADDR1 = data_to_flash(CONFIG_QUERY);
+	barrier();
+
+	result = *(u32 *)(blockStart + 2);
+	flash_read_array_amd32();
+	return !!result;
+
 }
 
 

CVS: blob/src/diag miniprint.c,NONE,1.1

[Stefan E. <se...@us...>]

Update of /cvsroot/blob/blob/src/diag
In directory usw-pr-cvs1:/tmp/cvs-serv24318/src/diag

Added Files:
	miniprint.c 
Log Message:
- miniprint board port by Urs Kaufmann


--- NEW FILE: miniprint.c ---
/*
 * miniprint.c: MINIPRINT specific stuff
 *
 * Copyright (C) 2002  Erik Mouw <J.A...@it...>
 * Modified for miniprint by Urs Kaufmann
 * $Id: miniprint.c,v 1.1 2002/05/27 13:05:05 seletz Exp $
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 */

#ident "$Id: miniprint.c,v 1.1 2002/05/27 13:05:05 seletz Exp $"

#ifdef HAVE_CONFIG_H
# include <blob/config.h>
#endif

#include <blob/init.h>
#include <blob/serial.h>




static void miniprint_init_hardware(void)
{
	/* select serial driver */
	serial_driver = &sa11x0_serial_driver;
}

__initlist(miniprint_init_hardware, INIT_LEVEL_DRIVER_SELECTION);

CVS: blob/src/blob miniprint.c,NONE,1.1

[Stefan E. <se...@us...>]

Update of /cvsroot/blob/blob/src/blob
In directory usw-pr-cvs1:/tmp/cvs-serv24318/src/blob

Added Files:
	miniprint.c 
Log Message:
- miniprint board port by Urs Kaufmann


--- NEW FILE: miniprint.c ---
/*
 * miniprint.c: FGAG miniprint  specific stuff
 *
 * Copyright (C) 2001  Erik Mouw (J.A...@it...)
 * Modified 2002 for Miniprint by Urs Kaufmann
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 */

#ident "$Id: miniprint.c,v 1.1 2002/05/27 13:05:05 seletz Exp $"

#ifdef HAVE_CONFIG_H
# include <blob/config.h>
#endif

#include <blob/flash.h>
#include <blob/init.h>
#include <blob/serial.h>

/* flash descriptor for Miniprint flash */
/* 2x Intel 28F128J3A strataflash (a 16MB) */
static flash_descriptor_t miniprint_flash_descriptors[] =
{
	{
		size: 2 * 128 * 1024,
		num: 64,
		lockable: 1
	},
	{
		/* NULL block */
	},
};

static void init_miniprint_flash_driver(void)
{
	flash_descriptors = miniprint_flash_descriptors;
	flash_driver = &intel32_flash_driver;
}
__initlist(init_miniprint_flash_driver, INIT_LEVEL_DRIVER_SELECTION);

static void miniprint_init_hardware(void)
{
	/* select serial driver */
	serial_driver = &sa11x0_serial_driver;
}
__initlist(miniprint_init_hardware, INIT_LEVEL_DRIVER_SELECTION);

CVS: blob/include/blob/arch miniprint.h,NONE,1.1

[Stefan E. <se...@us...>]

Update of /cvsroot/blob/blob/include/blob/arch
In directory usw-pr-cvs1:/tmp/cvs-serv24318/include/blob/arch

Added Files:
	miniprint.h 
Log Message:
- miniprint board port by Urs Kaufmann


--- NEW FILE: miniprint.h ---
/*
 * miniprint.h: miniprint specific defines
 *
 * Copyright (C) 2001  Erik Mouw (J.A...@it...)
 * Copyright (C) 2002  Urs Kaufmann <u_k...@bl...>
 * Copyright (C) 2002  Stefan Eletzhofer <ste...@el...>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 */

#ident "$Id: miniprint.h,v 1.1 2002/05/27 13:05:03 seletz Exp $"

#ifndef BLOB_ARCH_MINIPRINT_H
#define BLOB_ARCH_MINIPRINT_H

/* boot CPU speed */
#define CPU_SPEED		CPU_CORE_SPEED_206mhz	

/* serial port */
#define USE_SERIAL3

#define TERMINAL_SPEED baud_9600

/* GPIO for the LED */
#define LED_GPIO		(0x00000000) /* No LEDs */

/* the base address were BLOB is loaded by the first stage loader */
#define BLOB_ABS_BASE_ADDR	(0xc0200400)

/* where do various parts live in RAM */
#define BLOB_RAM_BASE		(0xc0100000)
#define KERNEL_RAM_BASE		(0xC0008000)
#define PARAM_RAM_BASE		(0xc0110000)
#define RAMDISK_RAM_BASE	(0xC0400000)

/* and where do they live in flash */
#define BLOB_FLASH_BASE         (0x00000000)
#define BLOB_FLASH_LEN          (256 * 1024)
#define PARAM_FLASH_BASE        (BLOB_FLASH_BASE + BLOB_FLASH_LEN)
#define PARAM_FLASH_LEN         (256 * 1024)
#define KERNEL_FLASH_BASE       (PARAM_FLASH_BASE + PARAM_FLASH_LEN)
#define KERNEL_FLASH_LEN        (1024 * 1024)
#define LOAD_RAMDISK            1 /* load ramdisk into ram */
#define RAMDISK_FLASH_BASE      (KERNEL_FLASH_BASE + KERNEL_FLASH_LEN)
#define RAMDISK_FLASH_LEN       (4 * 1024 * 1024)

/* the position of the kernel boot parameters */
#define BOOT_PARAMS		(0xc0000100)

/* the size (in kbytes) to which the compressed ramdisk expands */
#define RAMDISK_SIZE		(8 * 1024)

/* Memory configuration */
#ifdef BLOB_NEED_MEMCONFIG
#warning "use defines from memsetup.h for better readability"
#	define MDCNFG_VALUE  	0x0000b255		/* 0x0  MDCNFG */
#	define MDCAS00_VALUE	0xAAAAAA9F		/* 0x04 MDCAS00 */
#	define MDCAS01_VALUE	0xAAAAAAAA		/* 0x08 MDCAS01 */
#	define MDCAS02_VALUE	0xAAAAAAAA		/* 0x0c MDCAS02 */
#	define MSC0_VALUE	0x63726372		/* 0x10 MCS0 */
#	define MSC1_VALUE	0x2225fff9		/* 0x14 MCS1 */
#	define MECR_VALUE	0x21082108		/* 0x18 MECR  8-state Acces IO/Attr/Mem FAST = off (both Slots)*/
#	define MDREFR_VALUE	DO_NOT_USE_THIS_VALUE__GETS_AUTOMAGICALLY_COMPUTED
#	define MDCAS20_VALUE	0xAAAAAA9F		/* 0x20 MDCAS20 */
#	define MDCAS21_VALUE	0xAAAAAAAA		/* 0x24 MDCAS21 */
#	define MDCAS22_VALUE	0xAAAAAAAA		/* 0x28 MDCAS22 */
#	define MSC2_VALUE	0xfff8fff8		/* 0x2C MCS2 */
#	define SMCNFG_VALUE	0x00000000		/* 0x30 SMCNFG No SROM*/
#endif

#endif

CVS: blob/include/blob arch.h,1.8,1.9 lcd.h,1.5,1.6 linux.h,1.8,1.9

[Stefan E. <se...@us...>]

Update of /cvsroot/blob/blob/include/blob
In directory usw-pr-cvs1:/tmp/cvs-serv10621/include/blob

Modified Files:
	arch.h lcd.h linux.h 
Log Message:
- FGAG miniprint port by Urs Kaufmann


Index: arch.h
===================================================================
RCS file: /cvsroot/blob/blob/include/blob/arch.h,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -d -r1.8 -r1.9
--- arch.h	23 Apr 2002 12:36:19 -0000	1.8
+++ arch.h	27 May 2002 10:01:48 -0000	1.9
@@ -106,6 +106,8 @@
 # include <blob/arch/jornada720.h>
 #elif defined LART
 # include <blob/arch/lart.h>
+#elif defined MINIPRINT
+# include <blob/arch/miniprint.h>
 #elif defined NESA
 # include <blob/arch/nesa.h>
 #elif defined PLEB

Index: lcd.h
===================================================================
RCS file: /cvsroot/blob/blob/include/blob/lcd.h,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- lcd.h	11 Feb 2002 16:54:23 -0000	1.5
+++ lcd.h	27 May 2002 10:01:48 -0000	1.6
@@ -5,7 +5,8 @@
  *
  * Generic lcd framework
  *
- * Copyright (C) 2001 Stefan Eletzhofer <ste...@ww...>
+ * Copyright (C) 2001,2002 Stefan Eletzhofer <ste...@ww...>
+ * Copyright (C) 2002 Urs Kaufmann <u_k...@bl...>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -44,6 +45,49 @@
 #	define	LCD_VIDEORAM_END	(LCD_VIDEORAM_START + LCD_VIDEORAM_SIZE)
 #	define	LCD_VIDEORAM_DMA_ADR	(LCD_PALETTE_DMA_ADR + LCD_PALETTE_SIZE + (LCD_VIDEORAM_SIZE>>1))
 
+#elif MINIPRINT
+#       define  LCD_LCCR0       0x00000038
+/* LEN = 0   not enabled
+   CMS = 0   Color Mode
+   SDS = 0   Single Panel
+   LDM = 1   Done IRQ Disable
+   BAM = 1   Base Addr update IRQ disable
+   ERM = 1   Disable Error IRQ
+   PAS = 0   Passive Mode
+   BLE = 0   Little Endian
+   DPD = 0   for monochrome only
+   VSC = 0   Vert Slant
+   PDD = 0   No DMA Delay */
+#       define  LCD_LCCR1       0x01010530
+/* PPL = 304  (320-16=304)
+   HSW = 1    H-Sync
+   ELW = 1    EndOfLine Sync
+   BLW = 1    BeginOfLine Sync */
+#       define  LCD_LCCR2       0x000000EF
+/* LPP = 239   Lines
+   VSW = 0    Xtra Clock
+   EFW = 0    Xtra Clock
+   BFW = 0    Xtra Clock */
+#       define  LCD_LCCR3       0x0000FF1E
+/* PCD = 0x1E 75Hz Refresh
+   ACB = 0
+   API = 0
+   VSP = 0
+   HSP = 0
+   PCP = 0
+   OEP = 0  */
+#       define  LCD_BPP                 16
+#       define  LCD_COLS                320
+#       define  LCD_ROWS                240
+#       define  LCD_VIDEORAM_SIZE       ((LCD_BPP*LCD_ROWS*LCD_COLS)>>3)
+#       define  LCD_PALETTE_ENTRIES     256
+#       define  LCD_PALETTE_SIZE        (LCD_PALETTE_ENTRIES * 2)
+#       define  LCD_RAM_BASE            0xc0900000
+#       define  LCD_PALETTE_DMA_ADR     (LCD_RAM_BASE + 0x0)
+#       define  LCD_VIDEORAM_START      (LCD_RAM_BASE + LCD_PALETTE_SIZE)
+#       define  LCD_VIDEORAM_END        (LCD_VIDEORAM_START + LCD_VIDEORAM_SIZE)
+#       define  LCD_VIDEORAM_DMA_ADR    (LCD_PALETTE_DMA_ADR + LCD_PALETTE_SIZE + (LCD_VIDEORAM_SIZE>>1))
+# define  LCD_REVERSE
 #else
 #	error "Cowardly refusing to break your LCD, please supply correct LCD parameters."
 #endif
@@ -61,6 +105,9 @@
 
 int lcd_backlight_on( void );
 int lcd_backlight_off( void );
+
+int lcd_fill(int color);
+int lcd_set_pixel(unsigned int x, unsigned int y, unsigned int color);
 
 int lcd_palette_setup( void );
 

Index: linux.h
===================================================================
RCS file: /cvsroot/blob/blob/include/blob/linux.h,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -d -r1.8 -r1.9
--- linux.h	23 Apr 2002 12:36:19 -0000	1.8
+++ linux.h	27 May 2002 10:01:48 -0000	1.9
@@ -52,6 +52,8 @@
 # define ARCH_NUMBER (48)
 #elif defined LART
 # define ARCH_NUMBER (27)
+#elif defined MINIPRINT
+# define ARCH_NUMBER (173)
 #elif defined NESA
 # define ARCH_NUMBER (75)
 #elif defined PLEB

CVS: blob AUTHORS,1.9,1.10 acconfig.h,1.19,1.20 configure.in,1.52,1.53

[Stefan E. <se...@us...>]

Update of /cvsroot/blob/blob
In directory usw-pr-cvs1:/tmp/cvs-serv10621

Modified Files:
	AUTHORS acconfig.h configure.in 
Log Message:
- FGAG miniprint port by Urs Kaufmann


Index: AUTHORS
===================================================================
RCS file: /cvsroot/blob/blob/AUTHORS,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -d -r1.9 -r1.10
--- AUTHORS	13 May 2002 19:54:31 -0000	1.9
+++ AUTHORS	27 May 2002 10:01:47 -0000	1.10
@@ -88,3 +88,7 @@
 * Accelent IDP port
 ===================
 - Holger Schurig <h.s...@mn...>
+
+* FGAG miniprint port
+=====================
+- Urs Kaufmann <u_k...@bl...>

Index: acconfig.h
===================================================================
RCS file: /cvsroot/blob/blob/acconfig.h,v
retrieving revision 1.19
retrieving revision 1.20
diff -u -d -r1.19 -r1.20
--- acconfig.h	27 Apr 2002 06:55:09 -0000	1.19
+++ acconfig.h	27 May 2002 10:01:47 -0000	1.20
@@ -92,6 +92,9 @@
 /* Define for LART boards */
 #undef LART
 
+/* Define for MINIPRINT boards */
+#undef MINIPRINT
+
 /* Define for NESA boards */
 #undef NESA
 

Index: configure.in
===================================================================
RCS file: /cvsroot/blob/blob/configure.in,v
retrieving revision 1.52
retrieving revision 1.53
diff -u -d -r1.52 -r1.53
--- configure.in	27 Apr 2002 06:55:09 -0000	1.52
+++ configure.in	27 May 2002 10:01:47 -0000	1.53
@@ -203,6 +203,15 @@
 	use_cpu="sa1100"
 	use_lcd="no"
 	;;
+    miniprint)
+        board_name="FGAG miniprint"
+        AC_DEFINE(MINIPRINT)
+        BLOB_PLATFORM_OBJS="miniprint.o"
+        BLOB_FLASH_OBJS="intel32.o"   
+        DIAG_PLATFORM_OBJS="miniprint.o"
+        use_cpu="sa1110"
+        use_lcd="yes"
+        ;;
     nesa)
 	board_name="NESA"
 	AC_DEFINE(NESA)

CVS: blob/include/blob/arch Makefile.am,1.8,1.9

[Stefan E. <se...@us...>]

Update of /cvsroot/blob/blob/include/blob/arch
In directory usw-pr-cvs1:/tmp/cvs-serv10621/include/blob/arch

Modified Files:
	Makefile.am 
Log Message:
- FGAG miniprint port by Urs Kaufmann


Index: Makefile.am
===================================================================
RCS file: /cvsroot/blob/blob/include/blob/arch/Makefile.am,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -d -r1.8 -r1.9
--- Makefile.am	23 Apr 2002 12:36:19 -0000	1.8
+++ Makefile.am	27 May 2002 10:01:48 -0000	1.9
@@ -21,6 +21,7 @@
 	idr.h \
 	jornada720.h \
 	lart.h \
+	miniprint.h \
 	nesa.h \
 	pleb.h \
 	shannon.h \

CVS: blob/src/blob Makefile.am,1.30,1.31

[Stefan E. <se...@us...>]

Update of /cvsroot/blob/blob/src/blob
In directory usw-pr-cvs1:/tmp/cvs-serv10621/src/blob

Modified Files:
	Makefile.am 
Log Message:
- FGAG miniprint port by Urs Kaufmann


Index: Makefile.am
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/Makefile.am,v
retrieving revision 1.30
retrieving revision 1.31
diff -u -d -r1.30 -r1.31
--- Makefile.am	27 Apr 2002 06:55:09 -0000	1.30
+++ Makefile.am	27 May 2002 10:01:50 -0000	1.31
@@ -149,8 +149,8 @@
 	uucodec.c \
 	xmodem.c \
 	accelent_sa.c assabet.c brutus.c badge4.c clart.c frodo.c \
-	h3600.c idr.c jornada720.c lart.c nesa.c pleb.c shannon.c \
-	system3.c trizeps.c
+	h3600.c idr.c jornada720.c lart.c miniprint.c nesa.c pleb.c \
+	shannon.c system3.c trizeps.c
 
 
 blob_rest_elf32_DEPENDENCIES = \