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From: Stefan E. <se...@us...> - 2002-10-14 13:18:03
|
Update of /cvsroot/blob/blob/include/blob/arch In directory usw-pr-cvs1:/tmp/cvs-serv9483/include/blob/arch Modified Files: Makefile.am Added Files: cep.h Log Message: - integrated CEP patch sent by "Matej Sekoranja" <mat...@co...> --- NEW FILE: cep.h --- /* * cep.h: Cep specific defines * * Copyright (C) 2001 Erik Mouw (J.A...@it...) * * $Id: cep.h,v 1.1 2002/10/14 13:17:30 seletz Exp $ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA * */ #ident "$Id: cep.h,v 1.1 2002/10/14 13:17:30 seletz Exp $" #ifndef BLOB_ARCH_CEP_H #define BLOB_ARCH_CEP_H /* boot CPU speed */ #define CPU_SPEED (0x0b) /* use serial port 1 */ #define USE_SERIAL1 #define TERMINAL_SPEED baud_9600 /* GPIO for the LED */ #define LED_GPIO (0x00020000) /* GPIO 17 */ /* the base address were BLOB is loaded by the first stage loader */ #define BLOB_ABS_BASE_ADDR (0xc0200400) /* where do various parts live in RAM */ #define BLOB_RAM_BASE (0xc0100000) #define KERNEL_RAM_BASE (0xC0008000) #define PARAM_RAM_BASE (0xc0110000) #define RAMDISK_RAM_BASE (0xC0400000) /* and where do they live in flash */ #define BLOB_FLASH_BASE (0x00000000) #define BLOB_FLASH_LEN (256 * 1024) #define PARAM_FLASH_BASE (BLOB_FLASH_BASE + BLOB_FLASH_LEN) #define PARAM_FLASH_LEN (256 * 1024) #define KERNEL_FLASH_BASE (PARAM_FLASH_BASE + PARAM_FLASH_LEN) #define KERNEL_FLASH_LEN (1024 * 1024) #define LOAD_RAMDISK 1 /* load ramdisk into ram */ #define RAMDISK_FLASH_BASE (KERNEL_FLASH_BASE + KERNEL_FLASH_LEN) #define RAMDISK_FLASH_LEN (4 * 1024 * 1024) /* the position of the kernel boot parameters */ #define BOOT_PARAMS (0xc0000100) /* the size (in kbytes) to which the compressed ramdisk expands */ #define RAMDISK_SIZE (8 * 1024) /* Memory configuration */ #ifdef BLOB_NEED_MEMCONFIG #warning "use defines from memsetup.h for better readability" # define MDCNFG_VALUE 0x72547254 /* 0x0 MDCNFG */ # define MDCAS00_VALUE 0xAAAAAA7F /* 0x04 MDCAS00 */ # define MDCAS01_VALUE 0xAAAAAAAA /* 0x08 MDCAS01 */ # define MDCAS02_VALUE 0xAAAAAAAA /* 0x0c MDCAS02 */ # define MSC0_VALUE 0x4b384370 /* 0x10 MCS0 */ # define MSC1_VALUE 0x22212419 /* 0x14 MCS1 */ # define MECR_VALUE 0x994a994a /* 0x18 MECR */ # define MDREFR_VALUE DO_NOT_USE_THIS_VALUE__GETS_AUTOMAGICALLY_COMPUTED # define MDCAS20_VALUE 0xAAAAAA7F /* 0x20 MDCAS20 */ # define MDCAS21_VALUE 0xAAAAAAAA /* 0x24 MDCAS21 */ # define MDCAS22_VALUE 0xAAAAAAAA /* 0x28 MDCAS22 */ # define MSC2_VALUE 0x42196669 /* 0x2C MCS2 */ # define SMCNFG_VALUE 0xafccafcc /* 0x30 SMCNFG */ #endif #endif Index: Makefile.am =================================================================== RCS file: /cvsroot/blob/blob/include/blob/arch/Makefile.am,v retrieving revision 1.10 retrieving revision 1.11 diff -u -d -r1.10 -r1.11 --- Makefile.am 14 Aug 2002 20:57:56 -0000 1.10 +++ Makefile.am 14 Oct 2002 13:17:29 -0000 1.11 @@ -15,6 +15,7 @@ assabet.h \ badge4.h \ brutus.h \ + cep.h \ clart.h \ frodo.h \ h3600.h \ |
|
From: Stefan E. <se...@us...> - 2002-10-14 13:18:03
|
Update of /cvsroot/blob/blob/include/blob In directory usw-pr-cvs1:/tmp/cvs-serv9483/include/blob Modified Files: arch.h linux.h Log Message: - integrated CEP patch sent by "Matej Sekoranja" <mat...@co...> Index: arch.h =================================================================== RCS file: /cvsroot/blob/blob/include/blob/arch.h,v retrieving revision 1.10 retrieving revision 1.11 diff -u -d -r1.10 -r1.11 --- arch.h 14 Aug 2002 21:11:57 -0000 1.10 +++ arch.h 14 Oct 2002 13:17:28 -0000 1.11 @@ -42,6 +42,8 @@ # include <blob/arch/badge4.h> #elif defined BRUTUS # include <blob/arch/brutus.h> +#elif defined CEP +# include <blob/arch/cep.h> #elif defined CLART # include <blob/arch/clart.h> #elif defined FRODO Index: linux.h =================================================================== RCS file: /cvsroot/blob/blob/include/blob/linux.h,v retrieving revision 1.10 retrieving revision 1.11 diff -u -d -r1.10 -r1.11 --- linux.h 14 Aug 2002 21:11:57 -0000 1.10 +++ linux.h 14 Oct 2002 13:17:29 -0000 1.11 @@ -44,6 +44,8 @@ # define ARCH_NUMBER (148) #elif defined BRUTUS # define ARCH_NUMBER (16) +#elif defined CEP +# define ARCH_NUMBER (151) #elif defined CLART # define ARCH_NUMBER (68) #elif defined H3600 |
|
From: Stefan E. <se...@us...> - 2002-10-14 13:18:03
|
Update of /cvsroot/blob/blob
In directory usw-pr-cvs1:/tmp/cvs-serv9483
Modified Files:
AUTHORS acconfig.h configure.in
Log Message:
- integrated CEP patch sent by "Matej Sekoranja" <mat...@co...>
Index: AUTHORS
===================================================================
RCS file: /cvsroot/blob/blob/AUTHORS,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -d -r1.11 -r1.12
--- AUTHORS 14 Aug 2002 20:47:12 -0000 1.11
+++ AUTHORS 14 Oct 2002 13:17:24 -0000 1.12
@@ -101,3 +101,7 @@
===========================================
- Russell Geldmacher <rus...@in...>
+* Iskratel CEP port
+===================
+- Matej Sekoranja <mat...@co...>
+
Index: acconfig.h
===================================================================
RCS file: /cvsroot/blob/blob/acconfig.h,v
retrieving revision 1.21
retrieving revision 1.22
diff -u -d -r1.21 -r1.22
--- acconfig.h 14 Aug 2002 20:47:38 -0000 1.21
+++ acconfig.h 14 Oct 2002 13:17:26 -0000 1.22
@@ -74,6 +74,9 @@
/* Define for Brutus boards */
#undef BRUTUS
+/* Define for Iskratel CEP boards */
+#undef CEP
+
/* Define for CreditLART boards */
#undef CLART
Index: configure.in
===================================================================
RCS file: /cvsroot/blob/blob/configure.in,v
retrieving revision 1.54
retrieving revision 1.55
diff -u -d -r1.54 -r1.55
--- configure.in 14 Aug 2002 20:48:09 -0000 1.54
+++ configure.in 14 Oct 2002 13:17:27 -0000 1.55
@@ -79,6 +79,7 @@
neponset Intel Assabet with Neponset board
badge4 HPL Badge 4
brutus Intel Brutus
+ cep Iskratel CEP
creditlart CreditLART
frodo 2d3D, Inc. SA-1110 Development Board
h3600 Compaq Ipaq H36x0
@@ -147,6 +148,16 @@
use_cpu="sa1100"
use_lcd="no"
;;
+ cep)
+ board_name="Iskratel CEP"
+ AC_DEFINE(CEP)
+ BLOB_PLATFORM_OBJS="cep.o"
+ AC_MSG_WARN([Please check configuration in arch/cep.h])
+ BLOB_FLASH_OBJS="intel32.o"
+ DIAG_PLATFORM_OBJS="cep.o"
+ use_cpu="sa1110"
+ use_lcd="no"
+ ;;
creditlart)
board_name="Delft University of Technology CreditLART"
AC_DEFINE(CLART)
|
|
From: Stefan E. <se...@us...> - 2002-10-14 13:17:39
|
Update of /cvsroot/blob/blob/src/diag
In directory usw-pr-cvs1:/tmp/cvs-serv9483/src/diag
Modified Files:
Makefile.am
Added Files:
cep.c
Log Message:
- integrated CEP patch sent by "Matej Sekoranja" <mat...@co...>
--- NEW FILE: cep.c ---
/*
* cep.c: Cep specific stuff
*
* Copyright (C) 2002 Erik Mouw <J.A...@it...>
*
* $Id: cep.c,v 1.1 2002/10/14 13:17:33 seletz Exp $
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ident "$Id: cep.c,v 1.1 2002/10/14 13:17:33 seletz Exp $"
#ifdef HAVE_CONFIG_H
# include <blob/config.h>
#endif
#include <blob/init.h>
#include <blob/serial.h>
static void cep_init_hardware(void)
{
/* select serial driver */
serial_driver = &sa11x0_serial_driver;
}
__initlist(cep_init_hardware, INIT_LEVEL_DRIVER_SELECTION);
Index: Makefile.am
===================================================================
RCS file: /cvsroot/blob/blob/src/diag/Makefile.am,v
retrieving revision 1.17
retrieving revision 1.18
diff -u -d -r1.17 -r1.18
--- Makefile.am 14 Aug 2002 21:06:24 -0000 1.17
+++ Makefile.am 14 Oct 2002 13:17:32 -0000 1.18
@@ -60,6 +60,7 @@
assabet.c \
badge4.c \
brutus.c \
+ cep.c \
clart.c \
frodo.c \
h3600.c \
|
|
From: Stefan E. <se...@us...> - 2002-10-14 13:17:39
|
Update of /cvsroot/blob/blob/utils/build In directory usw-pr-cvs1:/tmp/cvs-serv9483/utils/build Modified Files: build_Makefile Log Message: - integrated CEP patch sent by "Matej Sekoranja" <mat...@co...> Index: build_Makefile =================================================================== RCS file: /cvsroot/blob/blob/utils/build/build_Makefile,v retrieving revision 1.13 retrieving revision 1.14 diff -u -d -r1.13 -r1.14 --- build_Makefile 14 Aug 2002 21:14:48 -0000 1.13 +++ build_Makefile 14 Oct 2002 13:17:34 -0000 1.14 @@ -13,7 +13,7 @@ # archs = \ - accelent_sa assabet badge4 brutus creditlart h3600 idr\ + accelent_sa assabet badge4 brutus cep creditlart h3600 idr\ jornada720 lart miniprint neponset nesa pleb shannon\ system3 frodo trizeps pxa_idp lubbock debug-archs = $(foreach a, $(archs), $(a)-debug) |
|
From: Abraham vd M. <ab...@2d...> - 2002-10-14 10:17:03
|
Hi Russell! > > That's what I gathered. However in the SDRAM SPD (Serial Presence Detec= t - > > the little EEPROM which contains the info about the DIMM) module, the > > refresh time goes from 3.9us up to 125us which is orders of magnitude > > shorter than all the other refresh times I've seen. >=20 > 64ms / 4096 =3D ~15us Thanks. That clears it up. One more question. You're currently ignoring the burst access times when configuring MDREFR. Isn't that dangerous? (if you have any bursts, its going to take too long to refresh and then the DRAM contents will corrupt) or am I missing something? Also, the SPD datasheet refers to SDRAM burst lengths of 1, 2, 4, 8 and full page. Is that 1,2,4,8 clocks? What is a full page? Is that across all the rows? Does it need multiple clock cycles to refresh a row (i.e. cas latency * rows =3D=3D longs burst access?) --=20 Regards Abraham * netgod opens his mailbox and immediately wishes he hadnt __________________________________________________________ Abraham vd Merwe - 2d3D, Inc. Device Driver Development, Outsourcing, Embedded Systems Cell: +27 82 565 4451 Snailmail: Tel: +27 21 761 7549 Block C, Aintree Park Fax: +27 21 761 7648 Doncaster Road Email: ab...@2d... Kenilworth, 7700 Http: http://www.2d3d.com South Africa |
|
From: Russell K. - A. L. <li...@ar...> - 2002-10-14 09:57:06
|
On Mon, Oct 14, 2002 at 11:26:58AM +0200, Abraham vd Merwe wrote: > That's what I gathered. However in the SDRAM SPD (Serial Presence Detect - > the little EEPROM which contains the info about the DIMM) module, the > refresh time goes from 3.9us up to 125us which is orders of magnitude > shorter than all the other refresh times I've seen. 64ms / 4096 = ~15us > So I've thought that the XXms refresh times was for all the rows Correct - you'll find this confirmed by data sheets on the actual SDRAM devices. > and that the SPD specs has it per row, but the explanation above throws > that theory out the door. Do you think > it is possible that the SDRAM dimms can have such short refresh times? No. Or if they do, the refresh starts severely impacting on the performance of the device. > Also, do those row address bits in above calculation include bits for the > bank selects or is it just the row address bits on the dimm (I guess it's > the latter right?) tbh I don't remember off hand. I seem to remember that it doesn't include the bank selects, but please check the data on the SDRAM chips you're using there. |
|
From: Abraham vd M. <ab...@2d...> - 2002-10-14 09:35:49
|
Hi Russell! > > The refresh time found in SDRAM SPD's - is that per row or for the whole > > module? Must be per row, since the longest possible refresh time is 125= us. >=20 > Tref is the time between refreshes on a single row of dynamic RAM. As > an example, take a Tref of 64ms and 12-bits of row address (ie, 4096 > rows.) >=20 > This means that row 0 must be refreshed every 64ms. Or to put it another > way, you need to refresh all rows in the chip within 64ms: >=20 > 0ms 64ms > v v > time: ------------------------------------> > rownr: 0 1 2 3 ... 4095 0 1 2 That's what I gathered. However in the SDRAM SPD (Serial Presence Detect - the little EEPROM which contains the info about the DIMM) module, the refresh time goes from 3.9us up to 125us which is orders of magnitude shorter than all the other refresh times I've seen. So I've thought that the XXms refresh times was for all the rows and that the SPD specs has it per row, but the explanation above throws that theory out the door. Do you think it is possible that the SDRAM dimms can have such short refresh times? See http://developer.intel.com/technology/memory/pc133sdram/spec/Spdsd12b.pdf byte 12 for the SPD refresh times. Also, do those row address bits in above calculation include bits for the bank selects or is it just the row address bits on the dimm (I guess it's the latter right?) --=20 Regards Abraham None love the bearer of bad news. -- Sophocles __________________________________________________________ Abraham vd Merwe - 2d3D, Inc. Device Driver Development, Outsourcing, Embedded Systems Cell: +27 82 565 4451 Snailmail: Tel: +27 21 761 7549 Block C, Aintree Park Fax: +27 21 761 7648 Doncaster Road Email: ab...@2d... Kenilworth, 7700 Http: http://www.2d3d.com South Africa |
|
From: Russell K. - A. L. <li...@ar...> - 2002-10-14 09:10:33
|
On Mon, Oct 14, 2002 at 10:17:40AM +0200, Abraham vd Merwe wrote:
> In arch/arm/mach-sa1110/cpu-sa1110.c I see that Russel seems to do
>
> (Tref >> rows) / 32
>
> where Tref is in clocks which makes sense apart from the bug (it should be /
> rows, not >> rows) and the fact that it doesn't take burst access into
> account.
That's not a bug. "rows" here is the number of address bits for a row
address. In the intel documentation, they're talking about the number
of rows - in other words 2^row_bits. So shifting right is the correct
thing to do in our case.
> The refresh time found in SDRAM SPD's - is that per row or for the whole
> module? Must be per row, since the longest possible refresh time is 125us.
Tref is the time between refreshes on a single row of dynamic RAM. As
an example, take a Tref of 64ms and 12-bits of row address (ie, 4096
rows.)
This means that row 0 must be refreshed every 64ms. Or to put it another
way, you need to refresh all rows in the chip within 64ms:
0ms 64ms
v v
time: ------------------------------------>
rownr: 0 1 2 3 ... 4095 0 1 2
|
|
From: Abraham vd M. <ab...@2d...> - 2002-10-14 08:33:01
|
Hi! Sorry for the cross post, but I'm not sure if all the BLOB developers are on the linux-arm-kernel mailinglists and this question involves them as well. I've got a StrongARM board with a DIMM on it and I can't figure out how to configure the DRI (see MDREFR register in SA-1110 dev manual) bitfield in the MDREFR. The StrongARM manual talks about ((Tref - Tburst) / rows) / Fmem) / 32 where Tref =3D refresh time of SDRAM Tburst =3D longest burst access in _any_ memory region Fmem =3D memory clock speed. rows =3D row address bits However they don't mention any units. Is Tref in ms? Tburst surely can't be in ms right in which case that equation doesn't make sens Is Fmem in Hz? Does the row address bits include the extra bank select bits or not? In arch/arm/mach-sa1110/cpu-sa1110.c I see that Russel seems to do (Tref >> rows) / 32 where Tref is in clocks which makes sense apart from the bug (it should be / rows, not >> rows) and the fact that it doesn't take burst access into account. The refresh time found in SDRAM SPD's - is that per row or for the whole module? Must be per row, since the longest possible refresh time is 125us. I'd really appreciate it if somebody could shed some light on this. --=20 Regards Abraham Teamwork is essential -- it allows you to blame someone else. __________________________________________________________ Abraham vd Merwe - 2d3D, Inc. Device Driver Development, Outsourcing, Embedded Systems Cell: +27 82 565 4451 Snailmail: Tel: +27 21 761 7549 Block C, Aintree Park Fax: +27 21 761 7648 Doncaster Road Email: ab...@2d... Kenilworth, 7700 Http: http://www.2d3d.com South Africa |
|
From: Jeff S. <je...@ac...> - 2002-10-11 14:10:11
|
-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 On Friday 11 October 2002 06:28 am, Holger Schurig wrote: > Hi everybody ! > > Does anybody know what FLYCNFG is? > @ Step 2c > @ fly-by-dma is defeatured on this part ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ There's your answer. Fly-by-dma was supposed to be part of the PXA-250 b= ut=20 they never got it working. Consequently, all references to it were delet= ed=20 in the later PXA developer's manuals. So, in effect, there is no such th= ing=20 as FLYCNFG. - --=20 Jeff Sutherland, Accelent Systems, Inc. <http://www.accelent.com> - + - + - + - + - + - + - + - + - + - + - + - =20 Kodachrome: After nearly 70 years there's still no better way to preserve an image. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.0.6 (GNU/Linux) Comment: For info see http://www.gnupg.org iD8DBQE9ptuwHuzovSc/o3oRAg2wAJ4wbn/RT/QsmNPzfgY65AMVolKwSQCfapxY eJYXEVd2eopNVJ7zfWtjstA=3D =3Dc4hd -----END PGP SIGNATURE----- |
|
From: Holger S. <h.s...@mn...> - 2002-10-11 11:21:26
|
Hi everybody ! Does anybody know what FLYCNFG is? In the "Intel PXA250 and PXA210 Application Processor Operating System Developer's Guide" from February 2002 it says in Chapter 10, Point 2. a. Write MSC0, MSC1, MSC2 b. Write MECR, MCMEM0... c. Write FLYCNFG But the "Intel PXA250 and PXA210 Application Processor Developer's Manual" from February 2000 does not contain the string FLYCNFG. The only reference that I found was in eCos (Redboot), in hal/arm/xscale/lubbock/current/include/hal_platform_setup.h #define FLYCNFG_OFFSET 0x20 and boards/cradle/memsetup.S @ Step 2c @ fly-by-dma is defeatured on this part @ write flycnfg @ldr r2, =CFG_FLYCNFG_VAL @str r2, [r1, #FLYCNFG_OFFSET] ... .set FLYCNFG_VAL , 0x01FE01FE @ Fly-by-DMA config. reg - NOT USED |
|
From: Stefan E. <se...@us...> - 2002-10-02 12:03:00
|
Update of /cvsroot/blob/blob/src/blob
In directory usw-pr-cvs1:/tmp/cvs-serv12855
Modified Files:
chkmem.c
Log Message:
- removed silly "test all mem regions" loop. This tested also
the region blob lives in --- KABOOM
- Provide 2 args (start-end) instead.
Index: chkmem.c
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/chkmem.c,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -d -r1.8 -r1.9
--- chkmem.c 11 Feb 2002 16:55:26 -0000 1.8
+++ chkmem.c 2 Oct 2002 12:02:56 -0000 1.9
@@ -138,14 +138,13 @@
int ChkMem( int argc, char *argv[] )
{
memtestfunc_t method;
- int area;
- u32 start = 0L;
- u32 end = 0L;
- u32 badaddr = 0L;
- u32 repcount = 0L;
+ u32 start = 0L;
+ u32 end = 0L;
+ u32 badaddr = 0L;
+ u32 repcount= 0L;
/* check args */
- if ( argc < 2 ) {
+ if ( argc < 4 ) {
SerialOutputString("*** not enough arguments\n");
return CHKMEM_ERR;
}
@@ -153,11 +152,21 @@
/* reset error counter */
chkmem_errs = 0;
+ if(strtou32(argv[1], &start) < 0) {
+ SerialOutputString("*** not a value (start)\n");
+ return CHKMEM_ERR;
+ }
+
+ if(strtou32(argv[2], &end) < 0) {
+ SerialOutputString("*** not a value (start)\n");
+ return CHKMEM_ERR;
+ }
+
/* get verbosity level */
showevery = CHKMEM_SHOWEVERY;
- if ( argc > 2 ) {
- if(strtou32(argv[2], &showevery) < 0) {
- SerialOutputString("*** not a value\n");
+ if ( argc > 4 ) {
+ if(strtou32(argv[4], &showevery) < 0) {
+ SerialOutputString("*** not a value (showevry)\n");
return CHKMEM_ERR;
}
@@ -171,20 +180,18 @@
/* get repeat count */
repcount = 1;
- if ( argc > 3 ) {
- if ( strtou32(argv[3], &repcount ) < 0 ) {
+ if ( argc > 5 ) {
+ if ( strtou32(argv[5], &repcount ) < 0 ) {
SerialOutputString("*** not a value\n");
return CHKMEM_ERR;
}
}
- SerialOutputString(argv[0]);
- SerialOutputString(": display every 0x");
- SerialOutputHex(showevery);
- SerialOutputString(" bytes\n");
+ printf( "%s: display every 0x%08x bytes\n", argv[0], showevery );
+ printf( "%s: start: 0x%08x end: 0x%08x\n", argv[0], start, end );
/* set memory test method */
- switch ( *argv[1] ) {
+ switch ( *argv[3] ) {
case '0':
method = ChkMemMovInv;
break;
@@ -201,16 +208,8 @@
}
while ( repcount-- ) {
- /* test all known memory areas */
- for (area = 0; area < NUM_MEM_AREAS; area++) {
- if(memory_map[area].used) {
- start = memory_map[area].start;
- end = start + memory_map[area].len;
-
- if ( method(start, end, 0x5555aaaa, &badaddr) != CHKMEM_OK ) {
- CHKMEM_PUSHERR( badaddr );
- }
- }
+ if ( method(start, end, 0x5555aaaa, &badaddr) != CHKMEM_OK ) {
+ CHKMEM_PUSHERR( badaddr );
}
}
@@ -222,7 +221,9 @@
return CHKMEM_OK;
}
-static char chkmemhelp[] = "chkmem [method] {verbosity:1..F} {repeat-count}\n"
+static char chkmemhelp[] = "chkmem start end method {verbosity:1..F} {repeat-count}\n"
+"start: startadr\n"
+"end: endadr\n"
"method=0: move-inverse test\n"
"method=1: address test\n"
"method=2: hardcore test\n"
@@ -288,10 +289,7 @@
SerialOutputString("\n*** memory errors:\n");
for ( i=0; i< chkmem_errs % CHKMEM_MAXERR; i++ ) {
- SerialOutputHex( i );
- SerialOutputString(": 0x");
- SerialOutputHex(chkmem_errlist[i]);
- SerialOutputString("\n");
+ printf( "%02d: adr 0x%08x\n", i, chkmem_errlist[i] );
}
return CHKMEM_OK;
@@ -333,11 +331,7 @@
SKIPBLOBMEM( start );
#if CHKMEM_DEBUG
- SerialOutputString("ChkMem: start(0x");
- SerialOutputHex(start);
- SerialOutputString(") - end(0x");
- SerialOutputHex(end);
- SerialOutputString(")\n");
+ printf( "chkmem: 0x%08x -> 0x%08x\n", start, end );
#endif
#if CHKMEM_DEBUG
@@ -422,11 +416,7 @@
SKIPBLOBMEM( start );
#if CHKMEM_DEBUG
- SerialOutputString("ChkMem: start(0x");
- SerialOutputHex(start);
- SerialOutputString(") - end(0x");
- SerialOutputHex(end);
- SerialOutputString(")\n");
+ printf( "chkmem: 0x%08x -> 0x%08x\n", start, end );
#endif
#if CHKMEM_DEBUG
@@ -489,11 +479,7 @@
SKIPBLOBMEM( start );
#if CHKMEM_DEBUG
- SerialOutputString("ChkMem: start(0x");
- SerialOutputHex(start);
- SerialOutputString(") - end(0x");
- SerialOutputHex(end);
- SerialOutputString(")\n");
+ printf( "chkmem: 0x%08x -> 0x%08x\n", start, end );
#endif
count = end - start;
|
|
From: Stefan E. <se...@us...> - 2002-10-02 11:25:11
|
Update of /cvsroot/blob/blob/src/blob In directory usw-pr-cvs1:/tmp/cvs-serv1534 Modified Files: memsetup-sa1110.S Log Message: - removed kernel include - we have _all_ defines in memsetup.h. If you need more, add them there. These defines are actually _different_ than their kernel counterparts. We use relative adressing here, and thus need offsets, not absolute values. DONT add new offsets to this file, please. Add them in memsetup.h instead. And please, absolutely DONT include kernel include files. They change. They will change again. Blob should be independant of the kernel source. Index: memsetup-sa1110.S =================================================================== RCS file: /cvsroot/blob/blob/src/blob/memsetup-sa1110.S,v retrieving revision 1.14 retrieving revision 1.15 diff -u -d -r1.14 -r1.15 --- memsetup-sa1110.S 25 Jul 2002 17:26:41 -0000 1.14 +++ memsetup-sa1110.S 2 Oct 2002 11:25:08 -0000 1.15 @@ -44,8 +44,16 @@ # include <blob/config.h> #endif +/*********************************************************************** + * NOTICE: + * PLEASE dont use kernel headers. Why? Because it fscks up everything + * as soon as they change. And yes, they change. And we're dependant of + * the kernel version the user has installed, and that's bad. + * + * We want blob to compile right out of the box. + * - stefan + */ #define __ASSEMBLY__ -#include <blob/sa1100.h> #define BLOB_NEED_MEMCONFIG #include <blob/memsetup.h> #include <blob/arch.h> @@ -53,14 +61,9 @@ .text .globl memsetup -MEM_REG_BASE: .long 0xa0000000 +MEM_REG_BASE: .long MEM_CONF_BASE MEM_START: .long MEMORY_START - -PWR_BASE: .long 0x90020000 -#define _PSSR 0x04 -#define _PSPR 0x08 -#define _PPCR 0x14 -#define _POSR 0x1C +PWR_BASE: .long PM_BASE /* Architecture headers can customized the memory setup behavior with * the following defines: @@ -106,6 +109,14 @@ ldr r0, MEM_REG_BASE adr r1, MEMORY_CONFIG + /* OK folks. These values are _offsets_ from + * MEM_REG_BASE and have _nothing_ to do with + * the kernel include file values, which defines + * them as _absolute_ values. + * + * The following works _only_ because the table above + * uses the same offsets. + */ ldr r2, [r1, #_MDCNFG ] str r2, [r0, #_MDCNFG ] @@ -142,7 +153,7 @@ /* Step 3: clear DH * NOTE: do NOT clear SSS, the kernel wants it set */ ldr r1, PWR_BASE - mov r2, #0x08 /* PSSR_DH */ + mov r2, #PSSR_DH str r2, [r1, #_PSSR] /* clear DH by writing 1 to it */ |
|
From: Stefan E. <se...@us...> - 2002-10-02 11:20:29
|
Update of /cvsroot/blob/blob/include/blob In directory usw-pr-cvs1:/tmp/cvs-serv32716 Modified Files: memsetup.h Log Message: - corrected defines to match chris' recent changes. NOTE: There seems a bit confusion here. The defines starting with _ (i.e. _PSSR etc.) are _offsets_ from a base address. This is to use relative adressing in assembly. The defines w/o the _ (i.e. PSSR etc.) are _absolute_ physical adresses. Index: memsetup.h =================================================================== RCS file: /cvsroot/blob/blob/include/blob/memsetup.h,v retrieving revision 1.10 retrieving revision 1.11 diff -u -d -r1.10 -r1.11 --- memsetup.h 26 Jul 2002 07:18:37 -0000 1.10 +++ memsetup.h 2 Oct 2002 11:20:27 -0000 1.11 @@ -36,19 +36,20 @@ * Memory Config Register Indices * based on 0xA0000000 */ -#define MDCNFG 0x0 -#define MDCAS00 0x04 -#define MDCAS01 0x08 -#define MDCAS02 0x0c -#define MCS0 0x10 -#define MCS1 0x14 -#define MECR 0x18 -#define MDREFR 0x1C -#define MDCAS20 0x20 -#define MDCAS21 0x24 -#define MDCAS22 0x28 -#define MCS2 0x2C -#define SMCNFG 0x30 +#define MEM_CONF_BASE 0xa0000000 +#define _MDCNFG 0x0 +#define _MDCAS00 0x04 +#define _MDCAS01 0x08 +#define _MDCAS02 0x0c +#define _MCS0 0x10 +#define _MCS1 0x14 +#define _MECR 0x18 +#define _MDREFR 0x1C +#define _MDCAS20 0x20 +#define _MDCAS21 0x24 +#define _MDCAS22 0x28 +#define _MCS2 0x2C +#define _SMCNFG 0x30 /********************************************************************** * MDCNFG masks @@ -126,5 +127,26 @@ #define MECR_BSA1(n_) (((n_)&0x1f)<<21) #define MECR_BSM1(n_) (((n_)&0x1f)<<26) #define MECR_FAST1 (1<<31) + +/********************************************************************** + * Power Manager (PM) registers + */ +#define PM_BASE 0x90020000 /* PM base */ +#define _PMCR 0x00 /* PM Control Reg. */ +#define _PSSR 0x04 /* PM Sleep Status Reg. */ +#define _PSPR 0x08 /* PM Scratch-Pad Reg. */ +#define _PWER 0x0C /* PM Wake-up Enable Reg. */ +#define _PCFR 0x10 /* PM general ConFiguration Reg. */ +#define _PPCR 0x14 /* PM PLL Configuration Reg. */ +#define _PGSR 0x18 /* PM GPIO Sleep state Reg. */ +#define _POSR 0x1C /* PM Oscillator Status Reg. */ + +#define PMCR_SF 0x00000001 /* Sleep Force (set only) */ + +#define PSSR_SS 0x00000001 /* Software Sleep */ +#define PSSR_BFS 0x00000002 /* Battery Fault Status */ +#define PSSR_VFS 0x00000004 /* Vdd Fault Status (VDD_FAULT) */ +#define PSSR_DH 0x00000008 /* DRAM control Hold */ +#define PSSR_PH 0x00000010 /* Peripheral control Hold */ #endif |
|
From: Stefan E. <se...@us...> - 2002-10-02 11:16:50
|
Update of /cvsroot/blob/blob/include/blob In directory usw-pr-cvs1:/tmp/cvs-serv32138 Added Files: bitfield.h Log Message: - our sa1111.h needs it. Either remove the macros there and remove this file, or keep both. |
|
From: Holger S. <h.s...@mn...> - 2002-08-16 10:28:33
|
The following patch disables all warnings of automake1.5:
Is it ok to submit this? (not sure if it would break old automake)
Index: configure.in
===================================================================
RCS file: /cvsroot/blob/blob/configure.in,v
retrieving revision 1.54
diff -u -b -B -w -p -r1.54 configure.in
--- configure.in 14 Aug 2002 20:48:09 -0000 1.54
+++ configure.in 16 Aug 2002 10:20:16 -0000
@@ -46,7 +46,10 @@ AC_CHECK_PROGS(CC, arm-linux-gcc gcc, ec
AC_CHECK_PROGS(OBJCOPY, arm-linux-objcopy objcopy, echo)
AC_CHECK_PROGS(RANLIB, arm-linux-ranlib ranlib, echo)
AC_CHECK_PROGS(AR, arm-linux-ar ar, echo)
-
+# Shuts up warnings of automake1.5 (and we use gcc as assembler)
+AC_CHECK_PROGS(AS, arm-linux-gcc gcc, echo)
+# Shuts up warnings of automake1.5
+AC_SUBST(ASFLAGS)
Index: src/blob/Makefile.am
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/Makefile.am,v
retrieving revision 1.32
diff -u -b -B -w -p -r1.32 Makefile.am
--- src/blob/Makefile.am 14 Aug 2002 21:04:23 -0000 1.32
+++ src/blob/Makefile.am 16 Aug 2002 10:20:16 -0000
@@ -32,7 +32,7 @@ bin_PROGRAMS = \
blob-chain
-INCLUDES += \
+INCLUDES = \
-I${top_builddir}/include \
-I${top_srcdir}/include
@@ -72,11 +72,11 @@ blob_start_elf32_DEPENDENCIES = \
@BLOB_STARTCODE_OBJS@ \
start-ld-script
-blob_start_elf32_LDFLAGS += \
+blob_start_elf32_LDFLAGS = \
-Wl,-T,${srcdir}/start-ld-script \
-Wl,-Map,blob-start-elf32.map
-blob_start_elf32_LDADD += \
+blob_start_elf32_LDADD = \
@BLOB_MEMSETUP_OBJS@ \
@BLOB_STARTCODE_OBJS@ \
-lgcc
@@ -85,7 +85,7 @@ blob_start_elf32_LDADD += \
blob_start_SOURCES =
-blob-start: blob-start-elf32
+blob-start$(EXEEXT): blob-start-elf32
$(OBJCOPY) $(OCFLAGS) $< $@
@@ -102,18 +102,18 @@ blob_start_chain_elf32_SOURCES = \
blob_start_chain_elf32_DEPENDENCIES =\
start-ld-script
-blob_start_chain_elf32_LDFLAGS += \
+blob_start_chain_elf32_LDFLAGS = \
-Wl,-T,${srcdir}/start-ld-script \
-Wl,-Map,blob-start-chain-elf32.map
-blob_start_chain_elf32_LDADD += \
+blob_start_chain_elf32_LDADD = \
-lgcc
blob_start_chain_SOURCES =
-blob-start-chain: blob-start-chain-elf32
+blob-start-chain$(EXEEXT): blob-start-chain-elf32
$(OBJCOPY) $(OCFLAGS) $< $@
@@ -171,12 +171,12 @@ blob_rest_elf32_DEPENDENCIES = \
rest-ld-script
-blob_rest_elf32_LDFLAGS += \
+blob_rest_elf32_LDFLAGS = \
-Wl,-T,rest-ld-script \
-Wl,-Map,blob-rest-elf32.map
-blob_rest_elf32_LDADD += \
+blob_rest_elf32_LDADD = \
@BLOB_CHKMEM_OBJS@ \
@BLOB_CLOCK_OBJS@ \
@BLOB_CRAMFS_OBJS@ \
@@ -193,7 +193,7 @@ blob_rest_elf32_LDADD += \
blob_rest_SOURCES =
-blob-rest: blob-rest-elf32
+blob-rest$(EXEXT): blob-rest-elf32
$(OBJCOPY) $(OCFLAGS) $< $@
@@ -204,7 +204,7 @@ blob-rest: blob-rest-elf32
blob_SOURCES =
-blob: blob-start blob-rest
+blob$(EXEEXT): blob-start blob-rest
rm -f $@
dd if=blob-start of=$@ bs=1k conv=sync
dd if=blob-rest of=$@ bs=1k seek=1
@@ -217,7 +217,7 @@ blob: blob-start blob-rest
blob_chain_SOURCES =
-blob-chain: blob-start-chain blob-rest
+blob-chain$(EXEXT): blob-start-chain blob-rest
rm -f $@
dd if=blob-start-chain of=$@ bs=1k conv=sync
dd if=blob-rest of=$@ bs=1k seek=1
Index: src/commands/Makefile.am
===================================================================
RCS file: /cvsroot/blob/blob/src/commands/Makefile.am,v
retrieving revision 1.5
diff -u -b -B -w -p -r1.5 Makefile.am
--- src/commands/Makefile.am 17 Apr 2002 19:39:50 -0000 1.5
+++ src/commands/Makefile.am 16 Aug 2002 10:20:16 -0000
@@ -41,7 +41,7 @@ libcommands_a_SOURCES = \
terminal.c
-INCLUDES += \
+INCLUDES = \
-I${top_builddir}/include \
-I${top_srcdir}/include
Index: src/diag/Makefile.am
===================================================================
RCS file: /cvsroot/blob/blob/src/diag/Makefile.am,v
retrieving revision 1.17
diff -u -b -B -w -p -r1.17 Makefile.am
--- src/diag/Makefile.am 14 Aug 2002 21:06:24 -0000 1.17
+++ src/diag/Makefile.am 16 Aug 2002 10:20:16 -0000
@@ -27,7 +27,7 @@ bin_PROGRAMS = \
diag
-INCLUDES += \
+INCLUDES = \
-I${top_builddir}/include \
-I${top_srcdir}/include
@@ -82,12 +82,12 @@ diag_elf32_DEPENDENCIES = \
${top_builddir}/src/lib/libblob.a \
ld-script
-diag_elf32_LDFLAGS += \
+diag_elf32_LDFLAGS = \
-Wl,-T,${srcdir}/ld-script \
-Wl,-Map,diag-elf32.map
-diag_elf32_LDADD += \
+diag_elf32_LDADD = \
@DIAG_LCD_OBJS@ \
@DIAG_PLATFORM_OBJS@ \
-L${top_builddir}/src/commands -L${top_builddir}/src/lib \
@@ -98,7 +98,7 @@ diag_elf32_LDADD += \
diag_SOURCES =
-diag: diag-elf32
+diag$(EXEEXT): diag-elf32
$(OBJCOPY) $(OCFLAGS) $< $@
Index: src/lib/Makefile.am
===================================================================
RCS file: /cvsroot/blob/blob/src/lib/Makefile.am,v
retrieving revision 1.22
diff -u -b -B -w -p -r1.22 Makefile.am
--- src/lib/Makefile.am 14 Aug 2002 21:13:45 -0000 1.22
+++ src/lib/Makefile.am 16 Aug 2002 10:20:16 -0000
@@ -56,7 +56,7 @@ libblob_a_DEPENDENCIES = \
libblob_a_LIBADD = \
@BLOB_SERIAL_DRIVER_OBJS@
-INCLUDES += \
+INCLUDES = \
-I${top_builddir}/include \
-I${top_srcdir}/include
|
|
From: Jeff S. <je...@us...> - 2002-08-14 21:17:39
|
Update of /cvsroot/blob/blob/include/blob In directory usw-pr-cvs1:/tmp/cvs-serv31281 Removed Files: pxa-regs.h Log Message: Lost in the reshuffling to add PXA support (no longer needed) --- pxa-regs.h DELETED --- |
|
From: Jeff S. <je...@us...> - 2002-08-14 21:14:51
|
Update of /cvsroot/blob/blob/utils/build In directory usw-pr-cvs1:/tmp/cvs-serv30220 Modified Files: build_all build_Makefile Log Message: Added support for PXA processors, Lubbock and PXA IDP machines Index: build_all =================================================================== RCS file: /cvsroot/blob/blob/utils/build/build_all,v retrieving revision 1.13 retrieving revision 1.14 diff -u -d -r1.13 -r1.14 --- build_all 27 May 2002 10:01:54 -0000 1.13 +++ build_all 14 Aug 2002 21:14:48 -0000 1.14 @@ -12,7 +12,7 @@ # published by the Free Software Foundation. # -archs="accelent_sa assabet badge4 brutus creditlart h3600 idr jornada720 lart miniprint neponset nesa pleb shannon system3 frodo trizeps" +archs="accelent_sa assabet badge4 brutus creditlart h3600 idr jornada720 lart lubbock miniprint neponset nesa pleb shannon system3 frodo trizeps pxa_idp" linux_prefix=~/LART/build/linux/elinux blob_src=~/src/sourceforge/blob extra_flags="--enable-all-features --with-commands=all" Index: build_Makefile =================================================================== RCS file: /cvsroot/blob/blob/utils/build/build_Makefile,v retrieving revision 1.12 retrieving revision 1.13 diff -u -d -r1.12 -r1.13 --- build_Makefile 27 May 2002 10:01:54 -0000 1.12 +++ build_Makefile 14 Aug 2002 21:14:48 -0000 1.13 @@ -15,7 +15,7 @@ archs = \ accelent_sa assabet badge4 brutus creditlart h3600 idr\ jornada720 lart miniprint neponset nesa pleb shannon\ - system3 frodo trizeps + system3 frodo trizeps pxa_idp lubbock debug-archs = $(foreach a, $(archs), $(a)-debug) all-archs = $(archs) $(debug-archs) |
|
From: Jeff S. <je...@us...> - 2002-08-14 21:13:48
|
Update of /cvsroot/blob/blob/src/lib
In directory usw-pr-cvs1:/tmp/cvs-serv29741
Modified Files:
Makefile.am led.c serial-pxa.c serial.c
Log Message:
Added support for PXA processors, Lubbock and PXA IDP machines
Index: Makefile.am
===================================================================
RCS file: /cvsroot/blob/blob/src/lib/Makefile.am,v
retrieving revision 1.21
retrieving revision 1.22
diff -u -d -r1.21 -r1.22
--- Makefile.am 10 May 2002 08:30:28 -0000 1.21
+++ Makefile.am 14 Aug 2002 21:13:45 -0000 1.22
@@ -43,7 +43,6 @@
printf.c \
reboot.c \
serial.c \
- serial-sa11x0.c \
strncpy.c \
strlen.c \
strncmp.c \
@@ -51,6 +50,11 @@
time.c \
util.c
+libblob_a_DEPENDENCIES = \
+ @BLOB_SERIAL_DRIVER_OBJS@
+
+libblob_a_LIBADD = \
+ @BLOB_SERIAL_DRIVER_OBJS@
INCLUDES += \
-I${top_builddir}/include \
Index: led.c
===================================================================
RCS file: /cvsroot/blob/blob/src/lib/led.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- led.c 15 Oct 2001 21:27:05 -0000 1.5
+++ led.c 14 Aug 2002 21:13:45 -0000 1.6
@@ -42,7 +42,6 @@
#include <blob/arch.h>
#include <blob/led.h>
-#include <blob/sa1100.h>
#include <blob/init.h>
@@ -61,25 +60,25 @@
-
+/* TODO: fix this */
void led_on(void)
{
if(led_locked)
return;
- GPSR = LED_GPIO;
+ /* GPSR = LED_GPIO; */
led_state = 1;
}
-
+/* TODO: fix this */
void led_off(void)
{
if(led_locked)
return;
- GPCR = LED_GPIO;
+ /* GPCR = LED_GPIO; */
led_state = 0;
}
Index: serial-pxa.c
===================================================================
RCS file: /cvsroot/blob/blob/src/lib/serial-pxa.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- serial-pxa.c 30 Jul 2002 17:45:18 -0000 1.2
+++ serial-pxa.c 14 Aug 2002 21:13:45 -0000 1.3
@@ -26,7 +26,6 @@
#include <blob/arch.h>
#include <blob/errno.h>
-#include <blob/pxa-regs.h>
#include <blob/serial.h>
#include <blob/types.h>
Index: serial.c
===================================================================
RCS file: /cvsroot/blob/blob/src/lib/serial.c,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -d -r1.9 -r1.10
--- serial.c 5 Feb 2002 14:47:54 -0000 1.9
+++ serial.c 14 Aug 2002 21:13:45 -0000 1.10
@@ -39,17 +39,10 @@
#include <blob/arch.h>
#include <blob/errno.h>
#include <blob/led.h>
-#include <blob/sa1100.h>
#include <blob/serial.h>
#include <blob/time.h>
-
-
-
serial_driver_t *serial_driver;
-
-
-
/* initialise serial port at the request baudrate. returns 0 on
* success, or a negative error number on failure
|
|
From: Jeff S. <je...@us...> - 2002-08-14 21:12:00
|
Update of /cvsroot/blob/blob/include/blob In directory usw-pr-cvs1:/tmp/cvs-serv28929 Modified Files: arch.h linux.h Log Message: Added support for PXA processors, Lubbock and PXA IDP machines Index: arch.h =================================================================== RCS file: /cvsroot/blob/blob/include/blob/arch.h,v retrieving revision 1.9 retrieving revision 1.10 diff -u -d -r1.9 -r1.10 --- arch.h 27 May 2002 10:01:48 -0000 1.9 +++ arch.h 14 Aug 2002 21:11:57 -0000 1.10 @@ -26,64 +26,12 @@ #ifndef BLOB_ARCH_H #define BLOB_ARCH_H - - - -/* memory start and end */ -#define MEMORY_START (0xc0000000) -#define MEMORY_END (0xe0000000) - - -/* - * CPU frequency table. - * - * See Section 8.2 (Core Clock Configuration Register) SA-1110 Developers - * Manual for more information. - * - * f_cpu = 16*f_osc + n*4*f_osc - * = 4*(n+4)*f_osc - * - * We have 3.6864-MHz oscillator. - * - * CCF[4:0] 3.6864-MHz Crystal Oscillator 3.5795-MHz Crystal Oscillator - * ------------------------------------------------------------------------- - * 00 59.0 57.3 - * 01 73.7 71.6 - * 02 88.5 85.9 - * 03 103.2 100.2 - * 04 118.0 114.5 - * 05 132.7 128.9 - * 06 147.5 143.2 - * 07 162.2 157.5 - * 08 176.9 171.8 - * 09 191.7 186.1 - * 0a 206.4 200.5 - * 0b 221.2 214.8 - * - * these are undocumented. - * - * 0c 235.9 ?? - * 0d 250.7 ?? - * 0e 265.4 ?? - * 0f 280.2 ?? - */ -#define CPU_CORE_SPEED_59mhz 0x00 -#define CPU_CORE_SPEED_73mhz 0x01 -#define CPU_CORE_SPEED_88mhz 0x02 -#define CPU_CORE_SPEED_103mhz 0x03 -#define CPU_CORE_SPEED_118mhz 0x04 -#define CPU_CORE_SPEED_132mhz 0x05 -#define CPU_CORE_SPEED_147mhz 0x06 -#define CPU_CORE_SPEED_162mhz 0x07 -#define CPU_CORE_SPEED_176mhz 0x08 -#define CPU_CORE_SPEED_191mhz 0x09 -#define CPU_CORE_SPEED_206mhz 0x0a -#define CPU_CORE_SPEED_221mhz 0x0b -#define CPU_CORE_SPEED_235mhz 0x0c -#define CPU_CORE_SPEED_250mhz 0x0d -#define CPU_CORE_SPEED_265mhz 0x0e -#define CPU_CORE_SPEED_280mhz 0x0f - +/* processor specific include files */ +#if defined PXA_IDP +#include <blob/proc/pxa.h> +#else +#include <blob/proc/sa11x0.h> +#endif /* architecture specific include files */ #if defined ACCELENT_SA @@ -106,6 +54,8 @@ # include <blob/arch/jornada720.h> #elif defined LART # include <blob/arch/lart.h> +#elif defined LUBBOCK +#include <blob/arch/lubbock.h> #elif defined MINIPRINT # include <blob/arch/miniprint.h> #elif defined NESA @@ -118,11 +68,10 @@ # include <blob/arch/system3.h> #elif defined TRIZEPS # include <blob/arch/trizeps.h> +#elif defined PXA_IDP +# include <blob/arch/pxa_idp.h> #else # error "Please add an architecture specific include file" #endif - - - #endif Index: linux.h =================================================================== RCS file: /cvsroot/blob/blob/include/blob/linux.h,v retrieving revision 1.9 retrieving revision 1.10 diff -u -d -r1.9 -r1.10 --- linux.h 27 May 2002 10:01:48 -0000 1.9 +++ linux.h 14 Aug 2002 21:11:57 -0000 1.10 @@ -34,6 +34,8 @@ #if defined ACCELENT_SA # define ARCH_NUMBER (22) +#elif defined PXA_IDP +# define ARCH_NUMBER (110) #elif defined ASSABET # define ARCH_NUMBER (25) #elif defined FRODO @@ -52,6 +54,8 @@ # define ARCH_NUMBER (48) #elif defined LART # define ARCH_NUMBER (27) +#elif defined LUBBOCK +# define ARCH_NUMBER (89) #elif defined MINIPRINT # define ARCH_NUMBER (173) #elif defined NESA |
|
From: Jeff S. <je...@us...> - 2002-08-14 21:07:58
|
Update of /cvsroot/blob/blob/tools In directory usw-pr-cvs1:/tmp/cvs-serv26723 Added Files: blob-real-clean Log Message: Some tools to help keep your CVS repository clean... --- NEW FILE: blob-real-clean --- #!/bin/bash if [ -f Makefile ] ; then make maintainer-clean-recursive fi rm -f configure config.status config.log aclocal.m4 INSTALL rm -rf autom4te-2.53.cache rm -f include/blob/config.h.in for f in `find . -name Makefile.in` do rm -f $f done for f in `find . -name "*~"` do rm -f $f done for f in `find . -name "#*#"` do rm -f $f done for f in `find . -name .deps` do rm -rf $f done cd tools rm -f config.guess rm -f config.sub rm -f depcomp rm -f install-sh rm -f missing rm -f mkinstalldirs |
|
From: Jeff S. <je...@us...> - 2002-08-14 21:06:26
|
Update of /cvsroot/blob/blob/src/diag
In directory usw-pr-cvs1:/tmp/cvs-serv26016
Modified Files:
Makefile.am
Added Files:
lubbock.c pxa_idp.c regs-pxa.c
Log Message:
Added support for PXA processors, Lubbock and PXA IDP machines
--- NEW FILE: lubbock.c ---
/*
* lubbock.c: Lubbock specific stuff
*
* Copyright (C) 2002 Intel Corporation
* Written by Rusty Geldmacher (rus...@in...)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifdef HAVE_CONFIG_H
# include <blob/config.h>
#endif
#include <blob/init.h>
#include <blob/serial.h>
static void assabet_init_hardware(void)
{
/* select serial driver */
serial_driver = &sa11x0_serial_driver;
}
__initlist(assabet_init_hardware, INIT_LEVEL_DRIVER_SELECTION);
--- NEW FILE: pxa_idp.c ---
/**********************************************************************
* accelent_sa.c
*
* Implements several POST routines for Accelent PXA-IDP platform
*
* Copyright (C) 2001 Stefan Eletzhofer <ste...@ww...>
* Copyright (c) 2002 Jeff Sutherland <je...@ac...>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/**********************************************************************
* Includes
*/
#ifdef HAVE_CONFIG_H
# include <blob/config.h>
#endif
#include <blob/types.h>
#include <blob/errno.h>
#include <blob/util.h>
#include <blob/command.h>
#include <blob/init.h>
#include <blob/serial.h>
#include <blob/time.h>
#include <blob/arch.h>
#define MEM(adr) (*((u32*)adr))
#define SET(reg,bit) ((reg) |= (1<<(bit)))
#define CLR(reg,bit) ((reg) &= ~(1<<(bit)))
static void pxa_idp_init_hardware(void)
{
/* select serial driver */
// also have to set up all gpio's here as well
serial_driver = &pxa_serial_driver;
}
__initlist(pxa_idp_init_hardware, INIT_LEVEL_DRIVER_SELECTION);
--- NEW FILE: regs-pxa.c ---
/*
* regs-sa11x0.c: command to nicely debug register contents
*
* Copyright (C) 2001 Stefan Eletzhofer <ste...@ww...>
* Copyright (C) 2002 Jeff Sutherland <je...@ac...>
*
* $Id: regs-pxa.c,v 1.1 2002/08/14 21:06:24 jeffs Exp $
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
/**********************************************************************
* includes
*/
#ifdef HAVE_CONFIG_H
# include <blob/config.h>
#endif
#include <blob/types.h>
#include <blob/errno.h>
#include <blob/util.h>
#include <blob/command.h>
#include <blob/init.h>
#include <blob/serial.h>
#include <blob/time.h>
#include <blob/arch.h>
/**********************************************************************
* defines
*/
#define MEM(adr) (*((u32*)adr))
#define SET(reg,bit) ((reg) |= (1<<(bit)))
#define CLR(reg,bit) ((reg) &= ~(1<<(bit)))
/**********************************************************************
* types
*/
/* a type to hold register infos */
typedef struct _reg {
char *name; /* reg name */
u32 adr; /* reg address */
char *desc; /* description */
} register_t;
/* a set of registers */
typedef struct _reg_set {
char *name; /* name of register set */
register_t *set; /* register set */
} reg_set_t;
/**********************************************************************
* module globals
*/
/* NOTE: the following register definitions are directly taken from
* linux/include/asm-arm/arch-sa1100/SA-1100.h
* and should therefore be correct.*/
/* Serial IF */
static register_t regs_uart[] = {
{ "Ser0UDCCR", (0x80000000), " Ser. port 0 UDC Control Reg. " },
{ "Ser0UDCAR", (0x80000004), " Ser. port 0 UDC Address Reg. " },
{ "Ser0UDCOMP", (0x80000008), " Ser. port 0 UDC Output Maximum Packet size reg. " },
{ "Ser0UDCIMP", (0x8000000C), " Ser. port 0 UDC Input Maximum Packet size reg. " },
{ "Ser0UDCCS0", (0x80000010), " Ser. port 0 UDC Control/Status reg. end-point 0 " },
{ "Ser0UDCCS1", (0x80000014), " Ser. port 0 UDC Control/Status reg. end-point 1 (output) " },
{ "Ser0UDCCS2", (0x80000018), " Ser. port 0 UDC Control/Status reg. end-point 2 (input) " },
{ "Ser0UDCD0", (0x8000001C), " Ser. port 0 UDC Data reg. end-point 0 " },
{ "Ser0UDCWC", (0x80000020), " Ser. port 0 UDC Write Count reg. end-point 0 " },
{ "Ser0UDCDR"// MSC0 (nCS0, nCS1) is for Flash
// MSC1 (nCS2, nCS3) is for ?, SA1111
// MSC2 (nCS4, nCS5) is for ExtBus, LCD
#define MSC0_VALUE 0x6c616c60
, (0x80000028), " Ser. port 0 UDC Data Reg. " },
{ "Ser0UDCSR", (0x80000030), " Ser. port 0 UDC Status Reg. " },
{ "_UTCR01", (0x80010000 + ((1) - 1)*0x00020000), " UART Control Reg. 0 [1..3] " },
{ "_UTCR02", (0x80010000 + ((2) - 1)*0x00020000), " UART Control Reg. 0 [1..3] " },
{ "_UTCR03", (0x80010000 + ((3) - 1)*0x00020000), " UART Control Reg. 0 [1..3] " },
{ "_UTCR11", (0x80010004 + ((1) - 1)*0x00020000), " UART Control Reg. 1 [1..3] " },
{ "_UTCR22", (0x80010008 + ((2) - 1)*0x00020000), " UART Control Reg. 2 [1..3] " },
{ "_UTCR33", (0x8001000C + ((3) - 1)*0x00020000), " UART Control Reg. 3 [1..3] " },
{ "_UTCR42", (0x80010010 + ((2) - 1)*0x00020000), " UART Control Reg. 4 [2] " },
{ "_UTDR1", (0x80010014 + ((1) - 1)*0x00020000), " UART Data Reg. [1..3] " },
{ "_UTDR2", (0x80010014 + ((2) - 1)*0x00020000), " UART Data Reg. [1..3] " },
{ "_UTDR3", (0x80010014 + ((3) - 1)*0x00020000), " UART Data Reg. [1..3] " },
{ "_UTSR01", (0x8001001C + ((1) - 1)*0x00020000), " UART Status Reg. 0 [1..3] " },
{ "_UTSR02", (0x8001001C + ((2) - 1)*0x00020000), " UART Status Reg. 0 [1..3] " },
{ "_UTSR03", (0x8001001C + ((3) - 1)*0x00020000), " UART Status Reg. 0 [1..3] " },
{ "_UTSR11", (0x80010020 + ((1) - 1)*0x00020000), " UART Status Reg. 1 [1..3] " },
{ "_UTSR12", (0x80010020 + ((2) - 1)*0x00020000), " UART Status Reg. 1 [1..3] " },
{ "_UTSR13", (0x80010020 + ((3) - 1)*0x00020000), " UART Status Reg. 1 [1..3] " },
{ "Ser1SDCR0", (0x80020060), " Ser. port 1 SDLC Control Reg. 0 " },
{ "Ser1SDCR1", (0x80020064), " Ser. port 1 SDLC Control Reg. 1 " },
{ "Ser1SDCR2", (0x80020068), " Ser. port 1 SDLC Control Reg. 2 " },
{ "Ser1SDCR3", (0x8002006C), " Ser. port 1 SDLC Control Reg. 3 " },
{ "Ser1SDCR4", (0x80020070), " Ser. port 1 SDLC Control Reg. 4 " },
{ "Ser1SDDR", (0x80020078), " Ser. port 1 SDLC Data Reg. " },
{ "Ser1SDSR0", (0x80020080), " Ser. port 1 SDLC Status Reg. 0 " },
{ "Ser1SDSR1", (0x80020084), " Ser. port 1 SDLC Status Reg. 1 " },
{ "Ser2HSCR0", (0x80040060), " Ser. port 2 HSSP Control Reg. 0 " },
{ "Ser2HSCR1", (0x80040064), " Ser. port 2 HSSP Control Reg. 1 " },
{ "Ser2HSDR", (0x8004006C), " Ser. port 2 HSSP Data Reg. " },
{ "Ser2HSSR0", (0x80040074), " Ser. port 2 HSSP Status Reg. 0 " },
{ "Ser2HSSR1", (0x80040078), " Ser. port 2 HSSP Status Reg. 1 " },
{ "Ser2HSCR2", (0x90060028), " Ser. port 2 HSSP Control Reg. 2 " },
{ "Ser4MCCR0", (0x80060000), " Ser. port 4 MCP Control Reg. 0 " },
{ "Ser4MCDR0", (0x80060008), " Ser. port 4 MCP Data Reg. 0 (audio) " },
{ "Ser4MCDR1", (0x8006000C), " Ser. port 4 MCP Data Reg. 1 (telecom) " },
{ "Ser4MCDR2", (0x80060010), " Ser. port 4 MCP Data Reg. 2 (CODEC reg.) " },
{ "Ser4MCSR", (0x80060018), " Ser. port 4 MCP Status Reg. " },
{ "Ser4MCCR1", (0x90060030), " Ser. port 4 MCP Control Reg. 1 " },
{ "Ser4SSCR0", (0x80070060), " Ser. port 4 SSP Control Reg. 0 " },
{ "Ser4SSCR1", (0x80070064), " Ser. port 4 SSP Control Reg. 1 " },
{ "Ser4SSDR", (0x8007006C), " Ser. port 4 SSP Data Reg. " },
{ "Ser4SSSR", (0x80070074), " Ser. port 4 SSP Status Reg. " },
{ NULL, 0 }
};
/* Timer */
static register_t regs_timer[] = {
{ "OSMR0", (0x90000000), " OS timer Match Reg. 0 " },
{ "OSMR1", (0x90000004), " OS timer Match Reg. 1 " },
{ "OSMR2", (0x90000008), " OS timer Match Reg. 2 " },
{ "OSMR3", (0x9000000c), " OS timer Match Reg. 3 " },
{ "OSCR", (0x90000010), " OS timer Counter Reg. " },
{ "OSSR", (0x90000014), " OS timer Status Reg. " },
{ "OWER", (0x90000018), " OS timer Watch-dog Enable Reg. " },
{ "OIER", (0x9000001C), " OS timer Interrupt Enable Reg. " },
{ NULL, 0 }
};
/* RTC and Power Mgmt */
static register_t regs_rtc[] = {
{ "RTAR", (0x90010000), " RTC Alarm Reg. " },
{ "RCNR", (0x90010004), " RTC CouNt Reg. " },
{ "RTTR", (0x90010008), " RTC Trim Reg. " },
{ "RTSR", (0x90010010), " RTC Status Reg. " },
{ "PMCR", (0x90020000), " PM Control Reg. " },
{ "PSSR", (0x90020004), " PM Sleep Status Reg. " },
{ "PSPR", (0x90020008), " PM Scratch-Pad Reg. " },
{ "PWER", (0x9002000C), " PM Wake-up Enable Reg. " },
{ "PCFR", (0x90020010), " PM general ConFiguration Reg. " },
{ "PPCR", (0x90020014), " PM PLL Configuration Reg. " },
{ "PGSR", (0x90020018), " PM GPIO Sleep state Reg. " },
{ "POSR", (0x9002001C), " PM Oscillator Status Reg. " },
{ "RSRR", (0x90030000), " RC Software Reset Reg. " },
{ "RCSR", (0x90030004), " RC Status Reg. " },
{ "TUCR", (0x90030008), " Test Unit Control Reg. " },
{ NULL, 0 }
};
/* GPIO / IRQ */
static register_t regs_gpio[] = {
{ "GPLR", (0x90040000), " GPIO Pin Level Reg. " },
{ "GPDR", (0x90040004), " GPIO Pin Direction Reg. " },
{ "GPSR", (0x90040008), " GPIO Pin output Set Reg. " },
{ "GPCR", (0x9004000C), " GPIO Pin output Clear Reg. " },
{ "GRER", (0x90040010), " GPIO Rising-Edge detect Reg. " },
{ "GFER", (0x90040014), " GPIO Falling-Edge detect Reg. " },
{ "GEDR", (0x90040018), " GPIO Edge Detect status Reg. " },
{ "GAFR", (0x9004001C), " GPIO Alternate Function Reg. " },
{ "ICIP", (0x90050000), " IC IRQ Pending reg. " },
{ "ICMR", (0x90050004), " IC Mask Reg. " },
{ "ICLR", (0x90050008), " IC Level Reg. " },
{ "ICCR", (0x9005000C), " IC Control Reg. " },
{ "ICFP", (0x90050010), " IC FIQ Pending reg. " },
{ "ICPR", (0x90050020), " IC Pending Reg. " },
{ "PPDR", (0x90060000), " PPC Pin Direction Reg. " },
{ "PPSR", (0x90060004), " PPC Pin State Reg. " },
{ "PPAR", (0x90060008), " PPC Pin Assignment Reg. " },
{ "PSDR", (0x9006000C), " PPC Sleep-mode pin Direction Reg. " },
{ "PPFR", (0x90060010), " PPC Pin Flag Reg. " },
{ NULL, 0 }
};
/* MEMORY */
static register_t regs_memory[] = {
{ "MDCNFG", (0xA0000000), " DRAM CoNFiGuration reg. " },
{ "MDCAS0", (0xA0000004), " DRAM CAS shift reg. 0 " },
{ "MDCAS1", (0xA0000008), " DRAM CAS shift reg. 1 " },
{ "MDCAS2", (0xA000000c), " DRAM CAS shift reg. 2 " },
{ "MSC0", (0xa0000010), " Static memory Control reg. 0 " },
{ "MSC1", (0xa0000014), " Static memory Control reg. 1 " },
{ "MSC2", (0xa000002c), " Static memory Control reg. 2, not contiguous " },
{ "MECR", (0xA0000018), " Expansion memory bus (PCMCIA) Configuration Reg. " },
{ "MDREFR", (0xA000001C), " (SA1110 only) DRAM Refresh Control Register" },
{ NULL, 0 }
};
/* LCD */
static register_t regs_lcd[] = {
{ "LCCR0", (0xB0100000), " LCD Control Reg. 0 " },
{ "LCSR", (0xB0100004), " LCD Status Reg. " },
{ "DBAR1", (0xB0100010), " LCD DMA Base Address Reg. channel 1 " },
{ "DCAR1", (0xB0100014), " LCD DMA Current Address Reg. channel 1 " },
{ "DBAR2", (0xB0100018), " LCD DMA Base Address Reg. channel 2 " },
{ "DCAR2", (0xB010001C), " LCD DMA Current Address Reg. channel 2 " },
{ "LCCR1", (0xB0100020), " LCD Control Reg. 1 " },
{ "LCCR2", (0xB0100024), " LCD Control Reg. 2 " },
{ "LCCR3", (0xB0100028), " LCD Control Reg. 3 " },
{ NULL, 0 }
};
/* TODO: add SA1111 companion chip registers */
/* finally the available register sets */
static reg_set_t reg_sets[] = {
{ "uart", regs_uart },
{ "timer", regs_timer },
{ "rtc", regs_rtc },
{ "gpio", regs_gpio },
{ "memory", regs_memory },
{ "lcd", regs_lcd },
{ NULL, NULL }
};
/**********************************************************************/
/**********************************************************************/
/**********************************************************************/
/**********************************************************************
* regs_show()
*
* AUTHOR: seletz
* REVISED:
*
* Display register contents
*
*/
static int regs_show( int argc, char *argv[] )
{
int i = 0;
int set = 0;
register_t *registers = NULL;
/* TODO: allow user to select a specific register set to
* print instead of simply print all sets. */
set = 0;
while ( reg_sets[set].name ) {
i = 0;
registers = reg_sets[set].set;
printf( "%s\n", reg_sets[set].name );
printf( "--------------------------------\n" );
while ( registers && registers[i].name ) {
printf( "%s= 0x%08x %s\n", registers[i].name, MEM( registers[i].adr ),
registers[i].desc?registers[i].desc:"" );
i++;
}
set++;
serial_write( '\n' );
}
return 0;
}
static char regshelp[] = "print register info\n";
__commandlist(regs_show, "regs", regshelp);
Index: Makefile.am
===================================================================
RCS file: /cvsroot/blob/blob/src/diag/Makefile.am,v
retrieving revision 1.16
retrieving revision 1.17
diff -u -d -r1.16 -r1.17
--- Makefile.am 27 May 2002 10:01:53 -0000 1.16
+++ Makefile.am 14 Aug 2002 21:06:24 -0000 1.17
@@ -66,12 +66,14 @@
idr.c \
jornada720.c \
lart.c \
+ lubbock.c \
miniprint.c \
nesa.c \
pleb.c \
shannon.c \
system3.c \
- trizeps.c
+ trizeps.c \
+ pxa_idp.c
diag_elf32_DEPENDENCIES = \
@DIAG_LCD_OBJS@ \
|
|
From: Jeff S. <je...@us...> - 2002-08-14 21:04:32
|
Update of /cvsroot/blob/blob/src/blob
In directory usw-pr-cvs1:/tmp/cvs-serv24974
Modified Files:
Makefile.am main.c param_block.c start.S
Added Files:
lubbock.c memsetup-pxa250.S pxa_idp.c start-pxa.S
Log Message:
Added support for PXA processors, Lubbock and PXA IDP machines
--- NEW FILE: lubbock.c ---
/*
* lubbock.c: Lubbock specific stuff
*
* Copyright (C) 2002 Intel Corporation
* Written by Rusty Geldmacher (rus...@in...)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifdef HAVE_CONFIG_H
# include <blob/config.h>
#endif
#include <blob/flash.h>
#include <blob/init.h>
#include <blob/serial.h>
/* flash descriptor for Assabet flash */
/* 2x Intel 28F128J3A strataflash (16MB) */
static const flash_descriptor_t assabet_flash_descriptors[] =
{
{
size: 2 * 128 * 1024,
num: 64,
lockable: 1
},
{
/* NULL block */
},
};
static void init_assabet_flash_driver(void)
{
flash_descriptors = assabet_flash_descriptors;
flash_driver = &intel32_flash_driver;
}
__initlist(init_assabet_flash_driver, INIT_LEVEL_DRIVER_SELECTION);
#define RS232_ENABLE 0x00001000
#define GREEN_LED_ENABLE 0x00004000
static void assabet_init_hardware(void)
{
u32 *bcr = (u32 *)0x12000000;
/* enable RS232 tranceiver and green LED */
*bcr = RS232_ENABLE | GREEN_LED_ENABLE;
/* select serial driver */
serial_driver = &sa11x0_serial_driver;
}
__initlist(assabet_init_hardware, INIT_LEVEL_DRIVER_SELECTION);
--- NEW FILE: memsetup-pxa250.S ---
/*
* Ripped from RedBoot, will add disclaimer later
*/
#ifdef HAVE_CONFIG_H
# include <blob/config.h>
#endif
#include <blob/arch.h>
.text
.globl memsetup
@****************************************************************************
@ Initlialize Memory Controller
@ The sequence below is based on the recommended init steps detailed in the
@ PXA Processor Developers Manual section 6.12
@
memsetup:
@ pause for 200 uSecs to allow internal clocks to settle
ldr r3, =OSCR_BASE_PHYSICAL @ reset the OS Timer Count to zero
mov r2, #0
str r2, [r3]
ldr r4, =0x300 @ really 0x2E1 is about 200usec,
@ so 0x300 should be plenty
1:
ldr r2, [r3]
cmp r4, r2
bgt 1b
@ get memory controller base address
ldr r1, =MEMC_BASE_PHYSICAL
@*****************************************************************************
@ Step 1
@
@ write msc0, read back to ensure data latches
@
ldr r2, =MSC0_VAL
str r2, [r1, #MSC0_OFFSET]
ldr r2, [r1, #MSC0_OFFSET]
@ write msc1
ldr r2, =MSC1_VAL
str r2, [r1, #MSC1_OFFSET]
ldr r2, [r1, #MSC1_OFFSET]
@ write msc2
ldr r2, =MSC2_VAL
str r2, [r1, #MSC2_OFFSET]
ldr r2, [r1, #MSC2_OFFSET]
@ write mecr
ldr r2, =MECR_VAL
str r2, [r1, #MECR_OFFSET]
@ write mcmem0
ldr r2, =MCMEM0_VAL
str r2, [r1, #MCMEM0_OFFSET]
@ write mcmem1
ldr r2, =MCMEM1_VAL
str r2, [r1, #MCMEM1_OFFSET]
@ write mcatt0
ldr r2, =MCATT0_VAL
str r2, [r1, #MCATT0_OFFSET]
@ write mcatt1
ldr r2, =MCATT1_VAL
str r2, [r1, #MCATT1_OFFSET]
@ write mcio0
ldr r2, =MCIO0_VAL
str r2, [r1, #MCIO0_OFFSET]
@ write mcio1
ldr r2, =MCIO1_VAL
str r2, [r1, #MCIO1_OFFSET]
@*********************************************************************
@ Step 1, 3rd bullet
@
@ get the mdrefr settings (k0run, e0pin, etc.)
ldr r3, =MDREFR_VAL
@ extract DRI field (we need a valid DRI field)
ldr r2, =0xFFF
@ valid DRI field in r3
and r3, r3, r2
@ get the reset state of MDREFR
ldr r4, [r1, #MDREFR_OFFSET]
@ clear the DRI field
bic r4, r4, r2
@ insert the valid DRI field loaded above
orr r4, r4, r3
@ write back mdrefr
str r4, [r1, #MDREFR_OFFSET]
@ *Note: preserve the mdrefr value in r4 *
@*****************************************************************************
@ Step 2
@ I dont know why, but this was commented out in RedBoot
@
@ fetch sxcnfg value
@
@ldr r2, =0
@ write back sxcnfg
@str r2, [r1, #SXCNFG_OFFSET]
@ if sxcnfg=0, do not program for synch-static memory
@cmp r2, #0
@beq 1f
@program sxmrs
@ldr r2, =SXMRS_SETTINGS
@str r2, [r1, #SXMRS_OFFSET]
@*****************************************************************************
@ Step 3
@ I am hard-coding in 50/100/300 clock speeds for now.
@ This needs testing since I hacked up a large, ugly version of this that was
@ Lubbock-specific. -Rusty
@
@ Assumes previous MDREFR value in r4, if not then read current MDREFR
@ clear the free-running clock bits
@ (clear K0Free, K1Free, K2Free)
bic r4, r4, #(0x00800000 | 0x01000000 | 0x02000000)
@ set K1RUN if bank 0 installed
orr r4, r4, #0x00010000
@ set K1DB2 (SDClk[1] = MemClk/2)
orreq r4, r4, #0x00020000
@ write back MDREFR
str r4, [r1, #MDREFR_OFFSET]
ldr r4, [r1, #MDREFR_OFFSET]
@ deassert SLFRSH
bic r4, r4, #0x00400000
@ write back MDREFR
str r4, [r1, #MDREFR_OFFSET]
@ assert E1PIN
orr r4, r4, #0x00008000
@ write back MDREFR
str r4, [r1, #MDREFR_OFFSET]
ldr r4, [r1, #MDREFR_OFFSET]
nop
nop
@*****************************************************************************
@ Step 4
@
@ fetch platform value of MDCNFG
ldr r2, =MDCNFG_VAL
@ disable all sdram banks
bic r2, r2, #(MDCNFG_DE0 | MDCNFG_DE1)
bic r2, r2, #(MDCNFG_DE2 | MDCNFG_DE3)
@ program banks 0/1 for bus width
bic r2, r2, #MDCNFG_DWID0_32B @ 0=32-bit
@ write initial value of MDCNFG, w/o enabling sdram banks
str r2, [r1, #MDCNFG_OFFSET]
@*****************************************************************************
@ Step 5
@
@ pause for 200 uSecs
ldr r3, =OSCR_BASE_PHYSICAL @ reset the OS Timer Count to zero
mov r2, #0
str r2, [r3]
ldr r4, =0x300 @ really 0x2E1 is about 200usec,
@ so 0x300 should be plenty
1:
ldr r2, [r3]
cmp r4, r2
bgt 1b
@*****************************************************************************
@ Step 6
@
@ turn everything off (caches off, MMU off, etc.)
mov r0, #0x78
mcr p15, 0, r0, c1, c0, 0
@*****************************************************************************
@ Step 7
@
@ Access memory *not yet enabled* for CBR refresh cycles (8)
@ CBR is generated for all banks
ldr r2, =SDRAM_BASE_PHYSICAL
str r2, [r2]
str r2, [r2]
str r2, [r2]
str r2, [r2]
str r2, [r2]
str r2, [r2]
str r2, [r2]
str r2, [r2]
@*****************************************************************************
@ Step 8: NOP (enable dcache if you wanna... we dont)
@
@*****************************************************************************
@ Step 9
@
@ get memory controller base address
ldr r1, =MEMC_BASE_PHYSICAL
@ fetch current mdcnfg value
ldr r3, [r1, #MDCNFG_OFFSET]
@ enable sdram bank 0 if installed (must do for any populated bank)
orr r3, r3, #MDCNFG_DE0
@ write back mdcnfg, enabling the sdram bank(s)
str r3, [r1, #MDCNFG_OFFSET]
@*****************************************************************************
@ Step 10
@
@ write MDMRS
ldr r2, =MDMRS_VAL
str r2, [r1, #MDMRS_OFFSET]
@*****************************************************************************
@ Step 11: Final Step
@ Omitted, used to contain work around for old A0 PXA250 stepping
@
@ return
mov pc, lr
--- NEW FILE: pxa_idp.c ---
/*
* accelent_sa.c: Accelent IDP specific stuff
*
* Copyright (C) 2001 Erik Mouw (J.A...@it...)
* Copyright (C) 2001 Stefan Eletzhofer
* (ste...@ww...)
* Copyright (C) 2002 Jeff Sutherland <je...@ac...>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
/**********************************************************************
* includes
*/
#ifdef HAVE_CONFIG_H
# include <blob/config.h>
#endif
#include <blob/main.h>
#include <blob/arch.h>
#include <blob/errno.h>
#include <blob/error.h>
#include <blob/util.h>
#include <blob/serial.h>
#include <blob/flash.h>
#include <blob/init.h>
#include <blob/command.h>
#include <blob/uucodec.h>
#include <blob/serial.h>
extern blob_status_t blob_status;
/* flash descriptor for Accelent IDP flash. */
/* Accelent PXA IDP uses 2xINTEL e28F128 Chips */
static const flash_descriptor_t accelent_sa_flash_descriptors[] =
{
{
size: 2 * 128 * 1024,
num: 128,
lockable: 1
},
{
/* NULL block */
},
};
static int accelent_sa_flash_enable_vpp(void)
{
//TODO
//set GPIO17
return 0;
}
static int accelent_sa_flash_disable_vpp(void)
{
//TODO
//reset GPIO17
return 0;
}
static void init_accelent_sa_flash_driver(void)
{
flash_descriptors = accelent_sa_flash_descriptors;
flash_driver = &intel32_flash_driver;
flash_driver->enable_vpp = accelent_sa_flash_enable_vpp;
flash_driver->disable_vpp = accelent_sa_flash_disable_vpp;
}
__initlist(init_accelent_sa_flash_driver, INIT_LEVEL_DRIVER_SELECTION);
static void accelent_sa_init_hardware(void)
{
/* select serial driver */
serial_driver = &pxa_serial_driver;
}
__initlist(accelent_sa_init_hardware, INIT_LEVEL_DRIVER_SELECTION);
/*********************************************************************
* cmd_download_file
*
* AUTOR: SELETZ
* REVISED:
*
* Download a file to arbitary memory location
*
*/
int cmd_download_file( int argc, char *argv[] )
{
int ret = 0;
u32 dest = 0L;
u32 len = 0L;
if ( argc < 3 ) return -EINVAL;
ret = strtou32( argv[1], &dest );
if ( ret < 0 ) return -EINVAL;
ret = strtou32( argv[2], &len );
if ( ret < 0 ) return -EINVAL;
if (blob_status.terminalSpeed != blob_status.downloadSpeed) {
SerialOutputString("Switching to download speed\n");
SerialOutputString("You have 60 seconds to switch your terminal emulator to the same speed and\n");
SerialOutputString("start downloading. After that " PACKAGE " will switch back to term speed.\n");
serial_init(blob_status.downloadSpeed);
} else {
SerialOutputString("You have 60 seconds to start downloading.\n");
}
ret = UUDecode((char *)dest, len);
if ( ret == len ) {
SerialOutputString("Received ");
SerialOutputDec(ret);
SerialOutputString(" (0x");
SerialOutputHex(ret);
SerialOutputString(") bytes.\n");
ret = 0;
} else {
SerialOutputString("error during uudecode\n");
}
if (blob_status.terminalSpeed != blob_status.downloadSpeed) {
SerialOutputString("\n(Please switch your terminal emulator back to terminal speed\n");
serial_init(blob_status.terminalSpeed);
}
return ret;
}
static char downloadhelp[] = "dlfile destadr filelength\n"
"download file to memory\n";
__commandlist( cmd_download_file, "dlfile", downloadhelp );
/*********************************************************************
* cmd_flash_write
*
* AUTOR: SELETZ
* REVISED:
*
* Command wrapper for low-level flash write access
*
*/
static int cmd_flash_write( int argc, char *argv[] )
{
int ret = 0;
u32 src = 0L;
u32 dest = 0L;
u32 len = 0L;
if ( argc < 4 ) return -EINVAL;
ret = strtou32( argv[1], &src );
if ( ret < 0 ) return -EINVAL;
ret = strtou32( argv[2], &dest );
if ( ret < 0 ) return -EINVAL;
ret = strtou32( argv[3], &len );
if ( ret < 0 ) return -EINVAL;
if ( len & (0x3) ) {
len = (len>>2) + 1;
} else {
len = len>>2;
}
_DBGU32( src );
_DBGU32( dest );
_DBGU32( len );
ret = flash_write_region( (u32 *)dest, (u32*)src, len );
return ret;
}
static char flashwritehelp[] = "fwrite srcadr destadr size(bytes)\n"
"flash a memory region\n";
__commandlist( cmd_flash_write, "fwrite", flashwritehelp );
/*********************************************************************
* cmd_flash_erase
*
* AUTOR: SELETZ
* REVISED:
*
* Command wrapper for low-level flash erasing
*
*/
static int cmd_flash_erase( int argc, char *argv[] )
{
int ret = 0;
u32 dest = 0L;
u32 len = 0L;
if ( argc < 3 ) return -EINVAL;
ret = strtou32( argv[1], &dest );
if ( ret < 0 ) return -EINVAL;
ret = strtou32( argv[2], &len );
if ( ret < 0 ) return -EINVAL;
if ( len & (0x3) ) {
len = (len>>2) + 1;
} else {
len = len>>2;
}
ret = flash_erase_region( (u32 *)dest, len );
return ret;
}
static char flasherasehelp[] = "ferase adr size(bytes)\n"
"erase a flash region\n";
__commandlist( cmd_flash_erase, "ferase", flasherasehelp );
--- NEW FILE: start-pxa.S ---
/*
* start-pxa: PXA (XScale) specific start code
*
* Copyright (C) 2002 Intel Corporation
* Written by Rusty Geldmacher (rus...@in...)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifdef HAVE_CONFIG_H
# include <blob/config.h>
#endif
#include <blob/arch.h>
.text
@ We start by implementing *all* exception vectors
@ Reset vector: this initialises the machine
@ note here that this not yet taken sleep wakeup into account -- lets just
@ get something to work first.
.globl reset
reset:
@ First, mask **ALL** interrupts
ldr r0, =ICMR
mov r1, #0x00
str r1, [r0]
real_reset:
#ifdef LUBBOCK
@ Lubbock must initialize GPIO before any chip selects will work.
bl gpio_init
@ now that chip selects will work, turn on lubbock HW registers, SRAM
@ and ethernet contoller chip selects
ldr r3, =MSC1
ldr r2, =MSC1_VAL
str r2, [r3]
ldr r2, [r3] @ need to read it back to latch it
#endif
bl ledinit
@ setup memory
bl memsetup
@ loop here infinitely until I can get this to compile and boot
@ TODO: get this to compile and boot.
crap:
b crap
@ turn off the LED. if it stays off it is an indication that
@ we didnt make it into the C code
bl led_off
@ everything is said and done over here, call normal_boot in
@ the generic startup code to continue the boot procedure
bl normal_boot
@ oops, normal_boot returns, something went wrong. signal an
@ error to the user
mov r6, #2
b endless_blink
/* we could choose to handle all exceptions in a nice way, but the
* best is to treat them as errors because blob should not contain
* errors
*/
/* Undefined instruction exception */
.globl undefined_instruction
undefined_instruction:
mov r6, #3
b endless_blink
/* SWI */
.globl software_interrupt
software_interrupt:
/* NOTE: This is NOT an error! If you think that blob should return
* from software interrupts, you're plain WRONG. The source of the
* problem is in the kernel: you should *disable* CONFIG_ANGELBOOT
* simply because blob is not angel. -- Erik
*/
mov r6, #4
b endless_blink
/* prefetch exception. shouldn't happen though we usually run with
* i-cache enabled */
.globl prefetch_abort
prefetch_abort:
mov r6, #5
b endless_blink
/* data abort */
.globl data_abort
data_abort:
mov r6, #6
b endless_blink
/* we *should* never reach this */
.globl not_used
not_used:
mov r6, #7
b endless_blink
/* interrupt. we could handle this differently later if some kind of
* driver in blob wants to be interrupt driven. for the time being we
* treat it as an error.
*/
.globl irq
irq:
mov r6, #8
b endless_blink
/* FIQ. same as IRQ */
.globl fiq
fiq:
mov r6, #9
b endless_blink
/* endless loop that blinks the LED. r6 contains the number of blinks */
endless_blink:
bl wait
mov r0, r6
bl led_blink
b endless_blink
wait:
/* busy wait loop*/
mov r5, #0x1000000
wait0:
subs r5, r5, #1
bne wait0
mov pc, lr
#ifdef LUBBOCK
@ initialize GPIO. This should be moved to its own file eventually...
init_gpio:
ldr r0, =GPSR0
ldr r1, =0x00008000
str r1, [r0]
ldr r0, =GPSR1
ldr r1, =0x00FC0382
str r1, [r0]
ldr r0, =GPSR2
ldr r1, =0x0001FFFF //0x0001C000
str r1, [r0]
ldr r0, =GPCR0
ldr r1, =0x00000000
str r1, [r0]
ldr r0, =GPCR1
ldr r1, =0x00000000
str r1, [r0]
ldr r0, =GPCR2
ldr r1, =0x00000000
str r1, [r0]
ldr r0, =GPDR0
ldr r1, =0x0060A800
str r1, [r0]
ldr r0, =GPDR1
ldr r1, =0x00FF0382
str r1, [r0]
ldr r0, =GPDR2
ldr r1, =0x0001C000
str r1, [r0]
ldr r0, =GAFR0_L
ldr r1, =0x98400000
str r1, [r0]
ldr r0, =GAFR0_U
ldr r1, =0x00002950
str r1, [r0]
ldr r0, =GAFR1_L
ldr r1, =0x000A9558
str r1, [r0]
ldr r0, =GAFR1_U
ldr r1, =0x0005AAAA
str r1, [r0]
ldr r0, =GAFR2_L
ldr r1, =0xA0000000
str r1, [r0]
ldr r0, =GAFR2_U
ldr r1, =0x00000002
str r1, [r0]
mov pc, lr
#endif
Index: Makefile.am
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/Makefile.am,v
retrieving revision 1.31
retrieving revision 1.32
diff -u -d -r1.31 -r1.32
--- Makefile.am 27 May 2002 10:01:50 -0000 1.31
+++ Makefile.am 14 Aug 2002 21:04:23 -0000 1.32
@@ -52,6 +52,9 @@
# ---- Blob first stage loader ---------------------------------------
+.S.o:
+ $(COMPILE) -D__ASSEMBLY__ -c $<
+
# WARNING: start.S *must* be the first file, otherwise the target will
# be linked in the wrong order!
blob_start_elf32_SOURCES = \
@@ -150,7 +153,7 @@
xmodem.c \
accelent_sa.c assabet.c brutus.c badge4.c clart.c frodo.c \
h3600.c idr.c jornada720.c lart.c miniprint.c nesa.c pleb.c \
- shannon.c system3.c trizeps.c
+ shannon.c system3.c trizeps.c pxa_idp.c
blob_rest_elf32_DEPENDENCIES = \
Index: main.c
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/main.c,v
retrieving revision 1.49
retrieving revision 1.50
diff -u -d -r1.49 -r1.50
--- main.c 2 May 2002 04:16:58 -0000 1.49
+++ main.c 14 Aug 2002 21:04:23 -0000 1.50
@@ -50,7 +50,6 @@
#include <blob/md5support.h>
#include <blob/memory.h>
#include <blob/param_block.h>
-#include <blob/sa1100.h>
#include <blob/serial.h>
#include <blob/time.h>
#include <blob/util.h>
Index: param_block.c
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/param_block.c,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -d -r1.7 -r1.8
--- param_block.c 21 Jan 2002 19:45:17 -0000 1.7
+++ param_block.c 14 Aug 2002 21:04:24 -0000 1.8
@@ -40,7 +40,7 @@
#include <blob/param_block.h>
#include <blob/main.h>
#include <blob/util.h>
-#include <blob/sa1100.h>
+
#if (defined(PARAM_START) && !defined(PARAM_LEN))
#error If PARAM_START is defined, PARAM_LEN must be too.
Index: start.S
===================================================================
RCS file: /cvsroot/blob/blob/src/blob/start.S,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -d -r1.9 -r1.10
--- start.S 19 Jul 2002 15:20:03 -0000 1.9
+++ start.S 14 Aug 2002 21:04:25 -0000 1.10
@@ -31,7 +31,7 @@
* [2] S. Furber, "ARM System Architecture", Addison Wesley Longman
* Ltd., Essex, England, 1996.
* [3] Intel Corporation, "Intel StrongARM SA-1110 Microprocessor
- * Advanced Developer's manual, December 1999
+ * Advanced Developer's manual", December 1999
*/
.ident "$Id$"
|
|
From: Jeff S. <je...@us...> - 2002-08-14 21:00:05
|
Update of /cvsroot/blob/blob/include/blob/proc In directory usw-pr-cvs1:/tmp/cvs-serv22850 Added Files: sa11x0.h Log Message: Added support for PXA processors, Lubbock and PXA IDP machines --- NEW FILE: sa11x0.h --- /* * proc/sa11x0.h - processor specific defines * * Copyright (C) 2001 Erik Mouw (J.A...@it...) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA * */ #ifndef BLOB_SA11X0_PROC_H #define BLOB_SA11X0_PROC_H /* memory start and end */ #define MEMORY_START (0xc0000000) #define MEMORY_END (0xe0000000) /* * CPU frequency table. * * See Section 8.2 (Core Clock Configuration Register) SA-1110 Developers * Manual for more information. * * f_cpu = 16*f_osc + n*4*f_osc * = 4*(n+4)*f_osc * * We have 3.6864-MHz oscillator. * * CCF[4:0] 3.6864-MHz Crystal Oscillator 3.5795-MHz Crystal Oscillator * ------------------------------------------------------------------------- * 00 59.0 57.3 * 01 73.7 71.6 * 02 88.5 85.9 * 03 103.2 100.2 * 04 118.0 114.5 * 05 132.7 128.9 * 06 147.5 143.2 * 07 162.2 157.5 * 08 176.9 171.8 * 09 191.7 186.1 * 0a 206.4 200.5 * 0b 221.2 214.8 * * these are undocumented. * * 0c 235.9 ?? * 0d 250.7 ?? * 0e 265.4 ?? * 0f 280.2 ?? */ #define CPU_CORE_SPEED_59mhz 0x00 #define CPU_CORE_SPEED_73mhz 0x01 #define CPU_CORE_SPEED_88mhz 0x02 #define CPU_CORE_SPEED_103mhz 0x03 #define CPU_CORE_SPEED_118mhz 0x04 #define CPU_CORE_SPEED_132mhz 0x05 #define CPU_CORE_SPEED_147mhz 0x06 #define CPU_CORE_SPEED_162mhz 0x07 #define CPU_CORE_SPEED_176mhz 0x08 #define CPU_CORE_SPEED_191mhz 0x09 #define CPU_CORE_SPEED_206mhz 0x0a #define CPU_CORE_SPEED_221mhz 0x0b #define CPU_CORE_SPEED_235mhz 0x0c #define CPU_CORE_SPEED_250mhz 0x0d #define CPU_CORE_SPEED_265mhz 0x0e #define CPU_CORE_SPEED_280mhz 0x0f #endif |
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