armadeus-commitlog Mailing List for armadeus (Page 88)

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- Log -----------------------------------------------------------------
commit 20a36f4c438d52e66b69f95cba9bec80c49aa9a3
Author: Gwenhael Goavec-Merou <gw...@tr...>
Date:   Thu Sep 22 17:42:22 2011 +0200

    Add spvision loader
    
    Signed-off-by: Gwenhael Goavec-Merou <gw...@tr...>

-----------------------------------------------------------------------

Summary of changes:
 .../linux/modules/fpga/virtual_components/Kconfig  |    1 +
 .../linux/modules/fpga/virtual_components/Makefile |    2 +-
 .../fpga/virtual_components/sploader/Kconfig       |    9 +
 .../fpga/virtual_components/sploader/Makefile      |    6 +
 .../fpga/virtual_components/sploader/sp-loader.c   |  386 ++++++++++++++++++++
 .../sploader/spartan_loadsecond.c                  |  384 +++++++++++++++++++
 .../sploader/spartan_loadsecond.h                  |  119 ++++++
 .../{led/led.h => sploader/sploader.h}             |   24 +-
 8 files changed, 919 insertions(+), 12 deletions(-)
 create mode 100644 target/linux/modules/fpga/virtual_components/sploader/Kconfig
 create mode 100644 target/linux/modules/fpga/virtual_components/sploader/Makefile
 create mode 100644 target/linux/modules/fpga/virtual_components/sploader/sp-loader.c
 create mode 100644 target/linux/modules/fpga/virtual_components/sploader/spartan_loadsecond.c
 create mode 100644 target/linux/modules/fpga/virtual_components/sploader/spartan_loadsecond.h
 copy target/linux/modules/fpga/virtual_components/{led/led.h => sploader/sploader.h} (66%)

diff --git a/target/linux/modules/fpga/virtual_components/Kconfig b/target/linux/modules/fpga/virtual_components/Kconfig
index cb048a7..c976c69 100644
--- a/target/linux/modules/fpga/virtual_components/Kconfig
+++ b/target/linux/modules/fpga/virtual_components/Kconfig
@@ -10,3 +10,4 @@ source "drivers/armadeus/fpga/virtual_components/irq_mngr/Kconfig"
 source "drivers/armadeus/fpga/virtual_components/button/Kconfig"
 source "drivers/armadeus/fpga/virtual_components/led/Kconfig"
 source "drivers/armadeus/fpga/virtual_components/pod_gpio/Kconfig"
+source "drivers/armadeus/fpga/virtual_components/sploader/Kconfig"
diff --git a/target/linux/modules/fpga/virtual_components/Makefile b/target/linux/modules/fpga/virtual_components/Makefile
index a2e2c2b..71d24a9 100644
--- a/target/linux/modules/fpga/virtual_components/Makefile
+++ b/target/linux/modules/fpga/virtual_components/Makefile
@@ -1,3 +1,3 @@
 
-obj-$(CONFIG_ARMADEUS_FPGA_VIRTUAL_COMPONENTS) += button/ irq_mngr/ led/ pod_gpio/
+obj-$(CONFIG_ARMADEUS_FPGA_VIRTUAL_COMPONENTS) += button/ irq_mngr/ led/ pod_gpio/ sploader/
 
diff --git a/target/linux/modules/fpga/virtual_components/sploader/Kconfig b/target/linux/modules/fpga/virtual_components/sploader/Kconfig
new file mode 100644
index 0000000..f99a9ac
--- /dev/null
+++ b/target/linux/modules/fpga/virtual_components/sploader/Kconfig
@@ -0,0 +1,9 @@
+
+config ARMADEUS_FPGA_VIRTUAL_SPVISION_LOADER
+	tristate "sploader"
+	default n
+	depends on ARMADEUS_FPGA_VIRTUAL_COMPONENTS
+	---help---
+	  With this driver you will be able to (re)load the
+	  configuration of your SP_VISION FPGA directly from
+	  Linux userspace
diff --git a/target/linux/modules/fpga/virtual_components/sploader/Makefile b/target/linux/modules/fpga/virtual_components/sploader/Makefile
new file mode 100644
index 0000000..03f0c9c
--- /dev/null
+++ b/target/linux/modules/fpga/virtual_components/sploader/Makefile
@@ -0,0 +1,6 @@
+#
+# Makefile for the Armadeus FPGA SP_VISION loader
+#
+
+obj-$(CONFIG_ARMADEUS_FPGA_VIRTUAL_SPVISION_LOADER) := sploader.o
+sploader-objs := spartan_loadsecond.o sp-loader.o
diff --git a/target/linux/modules/fpga/virtual_components/sploader/sp-loader.c b/target/linux/modules/fpga/virtual_components/sploader/sp-loader.c
new file mode 100644
index 0000000..15310ce
--- /dev/null
+++ b/target/linux/modules/fpga/virtual_components/sploader/sp-loader.c
@@ -0,0 +1,386 @@
+/*
+ * Generic Xilinx FPGA loader
+ *
+ * Copyright (C) 2006-2009 Julien Boibessot <jul...@ar...>
+ *                         Nicolas Colombain <nic...@ar...>
+ *                         Armadeus Project / Armadeus systems
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/* #define DEBUG */
+
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/proc_fs.h>
+#include <linux/fcntl.h>
+#include <linux/platform_device.h>
+#include <linux/miscdevice.h>
+#include <asm/uaccess.h>
+
+#include "spartan_loadsecond.h"
+
+/* request_mem_region */
+#include <linux/ioport.h>
+
+#include <mach/fpga.h>
+#include <mach/board-apf27.h>
+/* readw() writew() */
+#include <asm/io.h>
+#include "sploader.h"
+
+#define ARMADEUS_FPGA_BASE_ADDR_VIRT 0xF4300000
+#define DRIVER_VERSION		"0.91"
+#define DRIVER_NAME		"sp_loader"
+#define FPGA_PROC_DIRNAME	"driver/sp"
+#define FPGA_PROC_FILENAME	FPGA_PROC_DIRNAME "/sploader"
+#define FPGA_IOCTL 0x10000000	/* !! TO BE BETTER DEFINED !! */
+
+struct sploader_dev {
+	char *name;
+	void *membase;
+	struct resource *mem_res;
+};
+
+/* global variables */
+Xilinx_desc *g_current_desc = NULL;
+struct semaphore fpga_sema;
+
+static unsigned char fpga_descriptor = 0;	/* use default target_fpga_desc */
+module_param(fpga_descriptor, byte, 0);
+
+#define FPGA_BUFFER_SIZE 4096
+static unsigned char g_buffer[FPGA_BUFFER_SIZE];
+static unsigned char g_nb_users = 0;
+
+/* Handles write() done on /dev/fpga/loader */
+static ssize_t armadeus_fpga_write(struct file *file, const char *pData,
+				   size_t count, loff_t * f_pos)
+{
+	ssize_t ret = 0;
+
+	/* Get exclusive access */
+	if (down_interruptible(&fpga_sema))
+		return -ERESTARTSYS;
+
+	if (count > FPGA_BUFFER_SIZE) {
+		count = FPGA_BUFFER_SIZE;
+	}
+
+	/* Get value to write from user space */
+	ret = __copy_from_user(g_buffer, pData, count);
+	if (ret != 0) {
+		ret = -EFAULT;
+		goto out;
+	}
+
+	ret = write_content(g_current_desc, g_buffer, count);
+
+ out:
+	/* Release exclusive access */
+	up(&fpga_sema);
+
+	return ret;
+}
+
+static int armadeus_fpga_open(struct inode *inode, struct file *file)
+{
+	int ret;
+	u16 ip_id;
+
+	/* Get exclusive access */
+	if (down_interruptible(&fpga_sema))
+		return -ERESTARTSYS;
+
+	/* Only one access at a time is permitted */
+	if (g_nb_users > 0) {
+		ret = -EBUSY;
+		goto out;
+	}
+
+	/* check if ID is correct */
+	ip_id = readw(sdev->membase + pdata->idoffset);
+	if (ip_id != pdata->idnum) {
+		ret = -ENODEV;
+		printk(KERN_WARNING "For %s id:%d doesn't match with "
+						"id read %d,\n is device present ?\n",
+						pdata->name, pdata->idnum, ip_id);
+		goto out;
+	}
+
+	ret = loadsecond(g_current_desc);
+	if (!ret) {
+		printk("Starting FPGA download\n");
+		g_nb_users++;
+	}
+	pr_debug("Opening /dev/sp_loader, %d %d\n", fpga_descriptor, ret);
+
+ out:
+	/* Release exclusive access */
+	up(&fpga_sema);
+
+	return ret;
+}
+
+static int armadeus_fpga_release(struct inode *inode, struct file *file)
+{
+	if (end_load(g_current_desc)) {
+		printk("Failed to load FPGA !\n");
+	}
+
+	pr_debug("Closing access to /dev/fpgaloader\n");
+
+	if (g_nb_users > 0)
+		g_nb_users--;
+
+	return 0;
+}
+
+/* PROC file */
+static int procfile_fpga_read(char *buffer, __attribute__ ((unused))
+			      char **start, off_t offset, int buffer_length,
+			      int *eof, __attribute__ ((unused))
+			      void *data)
+{
+	int ret;
+
+	/* We give all of our information in one go, so if the user asks us if
+	   we have more information the answer should always be no.
+	   This is important because the standard read function from the
+	   library would continue to issue the read system call until the
+	   the kernel replies that it has no more information, or until 
+	   its buffer is filled */
+	if (offset > 0) {
+		/* we have finished to read, return 0 */
+		ret = 0;
+	} else {
+		//ret = fpga_get_infos(g_current_desc, buffer);
+	}
+
+	return ret;
+}
+
+static int procfile_fpga_write( __attribute__ ((unused))
+			       struct file *file,
+			       const char *buf, unsigned long count, void *data)
+{
+	return count;
+}
+
+/* Create /proc entries for direct access to FPGA config */
+static int create_proc_entries(void)
+{
+	static struct proc_dir_entry *fpga_Proc_File;
+
+	/* Create main directory */
+	proc_mkdir(FPGA_PROC_DIRNAME, NULL);
+
+	/* Create proc file */
+	fpga_Proc_File =
+	    create_proc_entry(FPGA_PROC_FILENAME,
+			      S_IWUSR | S_IRUSR | S_IRGRP | S_IROTH, NULL);
+	if (fpga_Proc_File == NULL) {
+		printk(DRIVER_NAME ": Could not register a" FPGA_PROC_FILENAME
+		       ". Terminating\n");
+		goto error;
+	} else {
+		fpga_Proc_File->read_proc = procfile_fpga_read;
+		fpga_Proc_File->write_proc = procfile_fpga_write;
+	}
+
+	return 0;
+ error:
+	remove_proc_entry(FPGA_PROC_DIRNAME, NULL);
+	return -ENOMEM;
+}
+
+static struct file_operations fpga_fops = {
+	.owner = THIS_MODULE,
+	.write = armadeus_fpga_write,
+	/*    .read    = armadeus_fpga_read, Configuration saving not supported yet */
+	.open = armadeus_fpga_open,
+	.release = armadeus_fpga_release,
+};
+
+static struct miscdevice fpgaloader_misc = {
+	.minor = MISC_DYNAMIC_MINOR,
+	.name = DRIVER_NAME,
+	.fops = &fpga_fops,
+};
+
+Xilinx_Spartan6_Slave_SelectMap_fns fpga_fns = {
+	.pre = fpga_spartan6_pre_fn,
+	.pgm = fpga_spartan6_pgm_fn,
+	.init = fpga_spartan6_init_fn,
+	.err = NULL,
+	.done = fpga_spartan6_done_fn,
+	.clk = fpga_spartan6_clk_fn,
+	.cs = fpga_spartan6_cs_fn,
+	.wr = fpga_spartan6_wr_fn,
+	.rdata = fpga_spartan6_rdata_fn,
+	.wdata = fpga_spartan6_wdata_fn,
+	.busy = fpga_spartan6_busy_fn,
+	.abort = fpga_spartan6_abort_fn,
+	.post = fpga_spartan6_post_fn,
+};
+
+#ifdef CONFIG_PM
+static int armadeus_sploader_suspend(struct platform_device *pdev,
+				     pm_message_t state)
+{
+	return 0;
+}
+
+static int armadeus_sploader_resume(struct platform_device *pdev)
+{
+	return 0;
+}
+#else
+#define armadeus_fpga_suspend   NULL
+#define armadeus_fpga_resume    NULL
+#endif
+
+static int armadeus_sploader_probe(struct platform_device *pdev)
+{
+	Xilinx_desc *pdata = pdev->dev.platform_data;
+	int ret = 0;
+	int result;
+	u16 data;
+	struct device *dev = &pdev->dev;
+	Xilinx_desc *platform_info;
+	struct resource *mem_res;
+	struct sploader_dev *sdev;
+
+	platform_info = dev->platform_data;
+	if (platform_info == NULL) {
+		dev_err(&pdev->dev, "probe - no platform data supplied\n");
+		result = -ENODEV;
+		goto err_no_pdata;
+	}
+	pdata->iface_fns = (void *)&fpga_fns;
+	/* Register the driver through misc layer to get MAJOR/MINOR */
+	result = misc_register(&fpgaloader_misc);
+	if (result) {
+		printk(KERN_ERR "%s:%u: misc_register failed %d\n",
+		       __func__, __LINE__, result);
+		goto err_no_pdata;
+	}
+
+	mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!mem_res) {
+		dev_err(&pdev->dev, "can't find mem resource\n");
+		return -EINVAL;
+	}
+
+	mem_res = request_mem_region(mem_res->start, resource_size(mem_res),
+				     "sploader");
+	if (!mem_res) {
+		dev_err(&pdev->dev, "iomem already in use\n");
+		return -EBUSY;
+	}
+
+	sdev = kmalloc(sizeof(struct sploader_dev), GFP_KERNEL);
+	if (!sdev) {
+		ret = -ENOMEM;
+		goto out_release_mem;
+	}
+
+	platform_info->ip_addr =
+	    ioremap(mem_res->start, resource_size(mem_res));
+	if (!sdev->membase) {
+		dev_err(&pdev->dev, "ioremap failed\n");
+		ret = -ENOMEM;
+		goto out_dev_free;
+	}
+
+	sdev->mem_res = mem_res;
+
+	data = readw(platform_info->ip_addr + platform_info->idoffset);
+	printk("ip num: %d idoffset: %d\n", data, platform_info->idoffset);
+
+	pdata->sdev = sdev;
+
+	result = create_proc_entries();
+	if (result < 0)
+		goto out_iounmap;
+
+	sema_init(&fpga_sema, 1);
+
+	/* initialize the current fpga descriptor with the one by default */
+	g_current_desc = platform_info;
+
+	printk(DRIVER_NAME " v" DRIVER_VERSION " ready\n");
+
+	return 0;
+
+ out_iounmap:
+	iounmap(platform_info->ip_addr);
+ out_dev_free:
+	kfree(sdev);
+ out_release_mem:
+	release_mem_region(mem_res->start, resource_size(mem_res));
+ err_no_pdata:
+
+	return ret;
+}
+
+static int armadeus_sploader_remove(struct platform_device *pdev)
+{
+	Xilinx_desc *dev = pdev->dev.platform_data;
+	struct sploader_dev *sdev = (*dev).sdev;
+
+	remove_proc_entry(FPGA_PROC_FILENAME, NULL);
+	remove_proc_entry(FPGA_PROC_DIRNAME, NULL);
+	misc_deregister(&fpgaloader_misc);
+	iounmap(g_current_desc->ip_addr);
+	kfree(sdev);
+	release_mem_region(sdev->mem_res->start, resource_size(sdev->mem_res));
+	printk(KERN_INFO "%s: deleted with success\n", dev->name);
+
+	return 0;
+}
+
+static struct platform_driver plat_sploader_driver = {
+	.probe = armadeus_sploader_probe,
+	.remove = armadeus_sploader_remove,
+	.suspend = armadeus_sploader_suspend,
+	.resume = armadeus_sploader_resume,
+	.driver = {
+		   .name = "sploader",
+		   .owner = THIS_MODULE,
+		   },
+};
+
+static int __init armadeus_spartan6_init(void)
+{
+	int ret;
+
+	printk("platform driver name %s\n", plat_sploader_driver.driver.name);
+	ret = platform_driver_register(&plat_sploader_driver);
+	return ret;
+}
+
+static void __exit armadeus_spartan6_exit(void)
+{
+	platform_driver_unregister(&plat_sploader_driver);
+}
+
+module_init(armadeus_spartan6_init);
+module_exit(armadeus_spartan6_exit);
+
+MODULE_AUTHOR("Julien Boibessot / Nicolas Colombain");
+MODULE_AUTHOR("Gwenhael Goavec-Merou");
+MODULE_DESCRIPTION("Armadeus SPVISION loading driver");
+MODULE_LICENSE("GPL");
diff --git a/target/linux/modules/fpga/virtual_components/sploader/spartan_loadsecond.c b/target/linux/modules/fpga/virtual_components/sploader/spartan_loadsecond.c
new file mode 100644
index 0000000..2e20238
--- /dev/null
+++ b/target/linux/modules/fpga/virtual_components/sploader/spartan_loadsecond.c
@@ -0,0 +1,384 @@
+#include <linux/types.h>
+#include "spartan_loadsecond.h"
+#include <asm/io.h>
+#include <linux/time.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+
+#define FPGA_FAIL -1
+#define FPGA_SUCCESS 0
+#define FALSE                    (0)
+#define TRUE                     (!FALSE)
+
+#define CONFIG_SYS_FPGA_WAIT        20000	/* 20 ms */
+#define CONFIG_FPGA_DELAY()
+
+#define SELECTMAP_CONFIG_RDWR_N     0
+#define SELECTMAP_CONFIG_PROGRAM_N  1
+#define SELECTMAP_CONFIG_CSI_N      2
+#define SELECTMAP_CONFIG_OS         3
+#define SELECTMAP_CONFIG_CLK        4
+#define SELECTMAP_CONFIG_REG        (desc->ip_addr+2)
+
+#define SELECTMAP_STATUS_DONE       0
+#define SELECTMAP_STATUS_BUSY       1
+#define SELECTMAP_STATUS_INIT_N     2
+#define SELECTMAP_STATUS_REG        (desc->ip_addr+4)
+#define SELECTMAP_DATA_REG          (desc->ip_addr+6)
+
+Xilinx_desc *xil_desc;
+
+/* Timeout function */
+static unsigned long get_timer(unsigned long initTime)
+{
+	struct timeval tv;
+	do_gettimeofday(&tv);
+	if (tv.tv_usec > initTime)	/* avoid overflow pb */
+		return tv.tv_usec - initTime;
+	else
+		return initTime - tv.tv_usec;
+}
+
+int fpga_spartan6_abort_fn(Xilinx_desc *desc, int cookie)
+{
+	int config;
+	//Xilinx_desc *desc = xil_desc;	//apf27_fpga_get_desc(cookie);
+	//config = ioread16(SELECTMAP_CONFIG_REG);	/* read config */
+	config = readw(SELECTMAP_CONFIG_REG);	/* read config */
+	config |= (1 << SELECTMAP_CONFIG_CLK);	/* IP in clock mode */
+	//iowrite16(config, SELECTMAP_CONFIG_REG);	/* write config */
+	writew(config, SELECTMAP_CONFIG_REG);	/* write config */
+	return cookie;
+}
+
+int fpga_spartan6_busy_fn(Xilinx_desc *desc, int cookie)
+{
+	u16 status;
+	//Xilinx_desc *desc = xil_desc;	//apf27_fpga_get_desc(cookie);
+
+	//status = ioread16(SELECTMAP_STATUS_REG);	/* read config */
+	status = readw(SELECTMAP_STATUS_REG);	/* read config */
+
+	return (((status & (1 << SELECTMAP_STATUS_BUSY)) != 0) ? 0 : 1);
+}
+
+int fpga_spartan6_post_fn(Xilinx_desc *desc, int cookie)
+{
+	int config;
+	//Xilinx_desc *desc = xil_desc;	//apf27_fpga_get_desc(cookie);
+
+	config = readw(SELECTMAP_CONFIG_REG);	/* read config */
+	config |= (1 << SELECTMAP_CONFIG_CLK);	/* IP in clock mode */
+	config &= ~(1 << SELECTMAP_CONFIG_OS);	/* OS High */
+	writew(config, SELECTMAP_CONFIG_REG);	/* write config */
+
+	return cookie;
+}
+
+int loadsecond(Xilinx_desc * desc)
+{
+	int ret_val;		// = FPGA_FAIL;     /* assume the worst */
+	Xilinx_Spartan6_Slave_SelectMap_fns *fn;
+	xil_desc = desc;
+	fn = desc->iface_fns;
+	ret_val = FPGA_FAIL;	/* assume the worst */
+
+	//desc->ip_addr = ip_addr;
+
+	printk("%s: start with interface functions @ 0x%p\n", __FUNCTION__, fn);
+	if (fn) {
+		int ret;
+		int cookie = desc->cookie;	/* make a local copy */
+		unsigned long ts;	/* timestamp */
+
+/*		printk("%s: Function Table:\n"
+		       "ptr:\t0x%p\n struct: 0x%p\n pre: 0x%p\n"
+		       "pgm:\t0x%p\n init:\t0x%p\n err:\t0x%p\n"
+		       "clk:\t0x%p\n cs:\t0x%p\n wr:\t0x%p\n"
+		       "read data:\t0x%p\n write data:\t0x%p\n"
+		       "busy:\t0x%p\n abort:\t0x%p\n",
+		       "post:\t0x%p\n\n",
+		       __FUNCTION__, &fn, fn, fn->pre, fn->pgm, fn->init,
+		       fn->err, fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata,
+		       fn->busy, fn->abort, fn->post);
+*/
+		/*
+		 * This code is designed to emulate the "Express Style"
+		 * Continuous Data Loading in Slave Parallel Mode for
+		 * the Spartan-VI Family.
+		 */
+		printk("Loading FPGA Device %d...\n", cookie);
+		/*
+		 * Run the pre configuration function if there is one.
+		 */
+		printk("Run pre function\n");
+		if (*fn->pre) {
+			ret = (*fn->pre) (desc, cookie);
+			if (ret < 0)
+				return FPGA_FAIL;
+		}
+
+		/* PROG_N low */
+		(*fn->pgm) (desc, TRUE, TRUE, cookie);	/* Assert the program, commit */
+
+		CONFIG_FPGA_DELAY();
+
+		/* PROG_N high */
+		(*fn->pgm) (desc, FALSE, TRUE, cookie);	/* deAssert the program, commit */
+
+		/* Wait for INIT_N low */
+		ts = get_timer(0);	/* get current time */
+		/* Now wait for INIT and BUSY to go high */
+		printk("/* Now wait for INIT and BUSY to go high */\n");
+		do {
+			CONFIG_FPGA_DELAY();
+
+			if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {	/* check the time */
+				printk
+				    ("** Timeout waiting for INIT to clear.\n");
+				(*fn->abort) (desc, cookie);	/* abort the burn */
+				return FPGA_FAIL;
+			}
+		} while ((*fn->init) (desc, cookie) == FPGA_SUCCESS);
+
+		printk("Assert write\n");
+		(*fn->wr) (desc, TRUE, TRUE, cookie);	/* Assert write, commit */
+
+		printk("ASSERT chip select\n");
+		(*fn->cs) (desc, TRUE, TRUE, cookie);	/* Assert chip select, commit */
+		printk("/* Load the data */\n");
+	}
+	return 0;
+}
+
+int write_content(Xilinx_desc * desc, void *buf, size_t bsize)
+{
+	unsigned long flags;
+	Xilinx_Spartan6_Slave_SelectMap_fns *fn = desc->iface_fns;
+
+	if (fn) {
+		int cookie = desc->cookie;	/* make a local copy */
+		size_t bytecount = 0;
+		unsigned char *data = (unsigned char *)buf;
+		/* Load the data */
+		raw_local_irq_save(flags);
+		while (bytecount < bsize) {
+			(*fn->wdata) (desc, data[bytecount], TRUE, cookie);	/* write the data */
+			bytecount++;
+		}
+		raw_local_irq_restore(flags);
+		return bsize;
+	}
+	return -EINVAL;
+}
+
+int end_load(Xilinx_desc * desc)
+{
+	int ret_val = FPGA_FAIL;	/* assume the worst */
+	Xilinx_Spartan6_Slave_SelectMap_fns *fn;
+//	xil_desc = desc;
+	fn = desc->iface_fns;
+	ret_val = FPGA_FAIL;	/* assume the worst */
+
+	if (fn) {
+		int cookie = desc->cookie;	/* make a local copy */
+		//size_t bytecount = 0;
+		//unsigned char *data = (unsigned char *)buf;
+		unsigned long ts;	/* timestamp */
+		/* now check for done signal */
+		printk("/* now check for done signal */\n");
+		ts = get_timer(0);	/* get current time */
+		ret_val = FPGA_SUCCESS;
+		while ((*fn->done) (desc, cookie) == FPGA_FAIL) {
+			/* XXX - we should have a check in here somewhere to
+			 * make sure we aren't busy forever... */
+
+			if (get_timer(ts) > 20000 /*CONFIG_SYS_FPGA_WAIT */ ) {	/* check the time */
+				printk
+				    ("** Timeout waiting for DONE to clear.\n");
+				(*fn->abort) (desc, cookie);	/* abort the burn */
+				ret_val = FPGA_FAIL;
+				break;
+			}
+		}
+
+		CONFIG_FPGA_DELAY();
+		printk("Deassert chip select\n");
+		(*fn->cs) (desc, FALSE, TRUE, cookie);	/* Deassert the chip select */
+		printk("Deassert write pin\n");
+		(*fn->wr) (desc, FALSE, TRUE, cookie);	/* Deassert the write pin */
+
+		printk("\n");	/* terminate the dotted line */
+
+		if (ret_val == FPGA_SUCCESS) {
+			printk("Done.\n");
+		}
+		/*
+		 * Run the post configuration function if there is one.
+		 */
+		if (*fn->post) {
+			(*fn->post) (desc, cookie);
+		} else {
+			printk("Fail.\n");
+		}
+	} else {
+		printk("%s: NULL Interface function table!\n", __FUNCTION__);
+	}
+	return ret_val;
+}
+
+int fpga_spartan6_init_fn(Xilinx_desc *desc, int cookie)
+{
+	uint16_t status;
+//	Xilinx_desc *desc = xil_desc;
+
+	status = readw(SELECTMAP_STATUS_REG);
+
+	printk("%s:%d: INIT check", __FUNCTION__, __LINE__);
+	printk("%d\n",
+	       (((status & (1 << SELECTMAP_STATUS_INIT_N)) == 0) ? 1 : 0));
+	printk("\n");
+
+	return (((status & (1 << SELECTMAP_STATUS_INIT_N)) ==
+		 0) ? FPGA_SUCCESS : FPGA_FAIL);
+}
+
+/*
+ *  * Set the FPGA's active-high clock line to the specified level
+ *   */
+int fpga_spartan6_clk_fn(Xilinx_desc *desc, int assert_clk, int flush, int cookie)
+{
+	printk("%s:%d: FPGA SET| CLOCK %s", __FUNCTION__, __LINE__,
+	       assert_clk ? "high" : "low");
+	printk("\n");
+
+	/* clock pulse is generated when a data is wrote */
+
+	return assert_clk;
+}
+
+/*
+ *  * Test the state of the active-high FPGA DONE pin
+ *   */
+int fpga_spartan6_done_fn(Xilinx_desc *desc, int cookie)
+{
+	uint16_t status;
+//	Xilinx_desc *desc = xil_desc;
+
+	status = readw(SELECTMAP_STATUS_REG);
+	return (((status & (1 << SELECTMAP_STATUS_DONE)) ==
+		 0) ? FPGA_FAIL : FPGA_SUCCESS);
+}
+
+/* TODO: read/write in 16bits mode */
+int fpga_spartan6_rdata_fn(Xilinx_desc *desc, unsigned char *data, int cookie)
+{
+//	Xilinx_desc *desc = xil_desc;	//apf27_fpga_get_desc(cookie);
+
+	*data = (readw(SELECTMAP_DATA_REG) & 0xff);
+	printk(".");
+
+	return *data;
+}
+
+int fpga_spartan6_wdata_fn(Xilinx_desc *desc, unsigned char data, 
+							int flush, int cookie)
+{
+	uint16_t val = data & 0x00ff;
+//	Xilinx_desc *desc = xil_desc;
+
+	writew(val, SELECTMAP_DATA_REG);
+
+	return data;
+}
+
+/* end of TODO */
+
+/*
+ *  * Set the FPGA's wr line to the specified level
+ *   */
+int fpga_spartan6_wr_fn(Xilinx_desc *desc, int assert_write, int flush, int cookie)
+{
+	unsigned short config;
+//	Xilinx_desc *desc = xil_desc;
+
+	printk("%s:%d: FPGA SET| RW %s ", __FUNCTION__, __LINE__,
+	       assert_write ? "high" : "low");
+	printk("\n");
+
+	config = readw(SELECTMAP_CONFIG_REG);
+	if (assert_write)
+		config &= ~(1 << SELECTMAP_CONFIG_RDWR_N);
+	else
+		config |= (1 << SELECTMAP_CONFIG_RDWR_N);
+	writew(config, SELECTMAP_CONFIG_REG);
+
+	return assert_write;
+}
+
+int fpga_spartan6_cs_fn(Xilinx_desc *desc, int assert_cs, int flush, int cookie)
+{
+	int config;
+//	Xilinx_desc *desc = xil_desc;
+
+	printk("%s:%d: FPGA SET| CS %s ", __FUNCTION__, __LINE__,
+	       assert_cs ? "high" : "low");
+	printk("\n");
+
+	config = readw(SELECTMAP_CONFIG_REG);
+	if (assert_cs)
+		config &= ~(1 << SELECTMAP_CONFIG_CSI_N);
+	else
+		config |= (1 << SELECTMAP_CONFIG_CSI_N);
+	writew(config, SELECTMAP_CONFIG_REG);
+
+	return assert_cs;
+}
+
+/*
+ *  * Initialize FPGA before download
+ *   */
+int fpga_spartan6_pre_fn(Xilinx_desc *desc, int cookie)
+{
+	int config;
+//	Xilinx_desc *desc = xil_desc;
+
+	config = readw(SELECTMAP_CONFIG_REG);
+	printk("config avant : %02x\n", config);
+	config &= ~(1 << SELECTMAP_CONFIG_CLK);	/* IP in selectmap mode */
+	config |= (1 << SELECTMAP_CONFIG_OS);	/* OS High */
+	config |= (1 << SELECTMAP_CONFIG_CSI_N);	/* CSI_n High */
+	config |= (1 << SELECTMAP_CONFIG_PROGRAM_N);	/* PROGRAM_n High */
+	config |= (1 << SELECTMAP_CONFIG_RDWR_N);	/* rdwr_n High */
+
+	writew(config, SELECTMAP_CONFIG_REG);
+	printk("valeur a ecrire : %02x\n", config);
+	udelay(1);		/*wait until supply started */
+	config = readw(SELECTMAP_CONFIG_REG);
+	printk("valeur apres : %02x\n", config);
+	return cookie;
+}
+
+/*
+ *  * Set the FPGA's active-low program line to the specified level
+ *   */
+int fpga_spartan6_pgm_fn(Xilinx_desc *desc, int assert, int flush, int cookie)
+{
+	unsigned short config;
+	//Xilinx_desc *desc = xil_desc;
+
+	config = readw(SELECTMAP_CONFIG_REG);
+
+	printk("%s:%d: FPGA SET PROGRAM %s", __FUNCTION__, __LINE__,
+	       assert ? "high" : "low");
+	printk("\n");
+
+	if (assert)
+		config &= ~(1 << SELECTMAP_CONFIG_PROGRAM_N);
+	else
+		config |= (1 << SELECTMAP_CONFIG_PROGRAM_N);
+
+	writew(config, SELECTMAP_CONFIG_REG);
+
+	return assert;
+}
diff --git a/target/linux/modules/fpga/virtual_components/sploader/spartan_loadsecond.h b/target/linux/modules/fpga/virtual_components/sploader/spartan_loadsecond.h
new file mode 100644
index 0000000..02bac57
--- /dev/null
+++ b/target/linux/modules/fpga/virtual_components/sploader/spartan_loadsecond.h
@@ -0,0 +1,119 @@
+#ifndef SPARTAN_LOADSECOND_H
+#define SPARTAN_LOADSECOND_H
+
+/* Xilinx types
+ *  *********************************************************************/
+struct sp_vision_struct {
+	uint32_t fpga_offset;
+	int ip_addr;
+	int ip_id;
+};
+
+typedef enum {			/* typedef Xilinx_iface */
+	min_xilinx_iface_type,	/* low range check value */
+	slave_serial,		/* serial data and external clock */
+	master_serial,		/* serial data w/ internal clock (not used) */
+	slave_parallel,		/* parallel data w/ external latch */
+	jtag_mode,		/* jtag/tap serial (not used ) */
+	master_selectmap,	/* master SelectMap (virtex2)           */
+	slave_selectmap,	/* slave SelectMap (virtex2)            */
+	max_xilinx_iface_type	/* insert all new types before this */
+} Xilinx_iface;			/* end, typedef Xilinx_iface */
+
+typedef enum {			/* typedef Xilinx_Family */
+	min_xilinx_type,	/* low range check value */
+	Xilinx_Spartan2,	/* Spartan-II Family */
+	Xilinx_VirtexE,		/* Virtex-E Family */
+	Xilinx_Virtex2,		/* Virtex2 Family */
+	Xilinx_Spartan3,	/* Spartan-III Family */
+	Xilinx_Spartan6,	/* Spartan-VI Family */
+	max_xilinx_type		/* insert all new types before this */
+} Xilinx_Family;		/* end, typedef Xilinx_Family */
+
+typedef struct {		/* typedef Xilinx_desc */
+	Xilinx_Family family;	/* part type */
+	Xilinx_iface iface;	/* interface type */
+	size_t size;		/* bytes of data part can accept */
+	void *iface_fns;	/* interface function table */
+	/* XXX:for second fpga configuration (throught first fpga) */
+	uint32_t fpga_offset;	/* first fpga offset */
+	void *ip_addr;		/* Address of spartan_selectmap IP */
+	int ip_id;		/* Idendifiant of spartan_selectmap IP */
+	/* end of XXX */
+	int cookie;		/* implementation specific cookie */
+	// ggm //
+	const char *name;             /* instance name  */
+	int num;                      /* instance number */
+	int idnum;                    /* identity number */
+	int idoffset;                 /* identity relative address */
+	struct sploader_dev *sdev;    /* struct for main device structure */
+
+} Xilinx_desc;			/* end, typedef Xilinx_desc */
+
+typedef int (*Xilinx_pgm_fn) (Xilinx_desc *desc, int assert_pgm, int flush, int cookie);
+typedef int (*Xilinx_init_fn) (Xilinx_desc *desc, int cookie);
+typedef int (*Xilinx_err_fn) (Xilinx_desc *desc, int cookie);
+typedef int (*Xilinx_done_fn) (Xilinx_desc *desc, int cookie);
+typedef int (*Xilinx_clk_fn) (Xilinx_desc *desc, int assert_clk, int flush, int cookie);
+typedef int (*Xilinx_cs_fn) (Xilinx_desc *desc, int assert_cs, int flush, int cookie);
+typedef int (*Xilinx_wr_fn) (Xilinx_desc *desc, int assert_write, int flush, int cookie);
+typedef int (*Xilinx_rdata_fn) (Xilinx_desc *desc, unsigned char *data, int cookie);
+typedef int (*Xilinx_wdata_fn) (Xilinx_desc *desc, unsigned char data, int flush, int cookie);
+typedef int (*Xilinx_busy_fn) (Xilinx_desc *desc, int cookie);
+typedef int (*Xilinx_abort_fn) (Xilinx_desc *desc, int cookie);
+typedef int (*Xilinx_pre_fn) (Xilinx_desc *desc, int cookie);
+typedef int (*Xilinx_post_fn) (Xilinx_desc *desc, int cookie);
+
+typedef struct {
+	Xilinx_pre_fn pre;
+	Xilinx_pgm_fn pgm;
+	Xilinx_init_fn init;
+	Xilinx_err_fn err;
+	Xilinx_done_fn done;
+	Xilinx_clk_fn clk;
+	Xilinx_cs_fn cs;
+	Xilinx_wr_fn wr;
+	Xilinx_rdata_fn rdata;
+	Xilinx_wdata_fn wdata;
+	Xilinx_busy_fn busy;
+	Xilinx_abort_fn abort;
+	Xilinx_post_fn post;
+	int relocated;
+} Xilinx_Spartan6_Slave_SelectMap_fns;
+
+#define FPGA_FAIL -1
+#define FPGA_SUCCESS 0
+#define FALSE                    (0)
+#define TRUE                     (!FALSE)
+#define SELECTMAP_CONFIG_REG        (desc->ip_addr+2)
+#define SELECTMAP_STATUS_REG        (desc->ip_addr+4)
+#define SELECTMAP_STATUS_BUSY       1
+
+#define SELECTMAP_CONFIG_CLK                4
+#define CONFIG_SYS_FPGA_WAIT            20000	/* 20 ms */
+#define CONFIG_FPGA_DELAY()
+#define SELECTMAP_STATUS_INIT_N     2
+#define SELECTMAP_STATUS_DONE       0
+#define SELECTMAP_DATA_REG  (desc->ip_addr+6)
+#define SELECTMAP_CONFIG_RDWR_N             0
+#define SELECTMAP_CONFIG_CSI_N              2
+#define SELECTMAP_CONFIG_PROGRAM_N  1
+
+int loadsecond(Xilinx_desc * desc/*, void *ip_addr, int ip_id*/);
+int write_content(Xilinx_desc * desc, void *buf, size_t bsize);
+int end_load(Xilinx_desc * desc);
+
+int fpga_spartan6_pre_fn(Xilinx_desc *desc, int cookie);
+int fpga_spartan6_pgm_fn(Xilinx_desc *desc, int assert_pgm, int flush, int cookie);
+int fpga_spartan6_cs_fn(Xilinx_desc *desc, int assert_cs, int flush, int cookie);
+int fpga_spartan6_init_fn(Xilinx_desc *desc, int cookie);
+int fpga_spartan6_done_fn(Xilinx_desc *desc, int cookie);
+int fpga_spartan6_clk_fn(Xilinx_desc *desc, int assert_clk, int flush, int cookie);
+int fpga_spartan6_wr_fn(Xilinx_desc *desc, int assert_write, int flush, int cookie);
+int fpga_spartan6_rdata_fn(Xilinx_desc *desc, unsigned char *data, int cookie);
+int fpga_spartan6_wdata_fn(Xilinx_desc *desc, unsigned char data, int flush, int cookie);
+int fpga_spartan6_abort_fn(Xilinx_desc *desc, int cookie);
+int fpga_spartan6_busy_fn(Xilinx_desc *desc, int cookie);
+int fpga_spartan6_post_fn(Xilinx_desc *desc, int cookie);
+
+#endif				/*SPARTAN_LOADSECOND_H */
diff --git a/target/linux/modules/fpga/virtual_components/led/led.h b/target/linux/modules/fpga/virtual_components/sploader/sploader.h
similarity index 66%
copy from target/linux/modules/fpga/virtual_components/led/led.h
copy to target/linux/modules/fpga/virtual_components/sploader/sploader.h
index 4762af4..6231fc3 100644
--- a/target/linux/modules/fpga/virtual_components/led/led.h
+++ b/target/linux/modules/fpga/virtual_components/sploader/sploader.h
@@ -1,5 +1,5 @@
 /*
- * Platform data for Wishbone LED IP driver
+ * Platform data for Wishbone SPLOADER IP driver
  *
  * (c) Copyright 2007-2011 The Armadeus Project - ARMadeus Systems
  * Fabien Marteau <fab...@ar...>
@@ -18,18 +18,20 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
-#ifndef __LED_H__
-#define __LED_H__
 
-#define LED_REG_OFFSET (0x00)
+#ifndef __SPLOADER_H__
+#define __SPLOADER_H__
+
+#define SPLOADER_REG_OFFSET (0x00)
 
 /* platform device */
-struct plat_led_port {
-	const char *name;	/* instance name  */
-	int num;		/* instance number */
-	int idnum;		/* identity number */
-	int idoffset;		/* identity relative address */
-	struct led_dev *sdev;	/* struct for main device structure*/
+struct plat_sploader_port
+{
+  const char *name;				/* instance name  */
+  int num;						/* instance number */
+  int idnum;					/* identity number */
+  int idoffset;					/* identity relative address */
+  struct sploader_dev *sdev;	/* struct for main device structure */
 };
 
-#endif /* __LED_H__ */
+#endif /* __SPLOADER_H__ */


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