[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.0-2495-g5c1e11a

[Julien B a. A. <ar...@us...>]

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- Log -----------------------------------------------------------------
commit 5c1e11ae7b587c5efa28e8af1854e31cc0c126da
Author: Julien Boibessot <jul...@ar...>
Date:   Fri Sep 2 12:23:22 2011 +0200

    [DEBUG] Add i.MX51 IIM registers to imxregs

-----------------------------------------------------------------------

Summary of changes:
 target/linux/debug/imxregs/imx51regs.h |   22 ++++++++++++++++++++++
 1 files changed, 22 insertions(+), 0 deletions(-)

diff --git a/target/linux/debug/imxregs/imx51regs.h b/target/linux/debug/imxregs/imx51regs.h
index 497b6c7..4d8d787 100644
--- a/target/linux/debug/imxregs/imx51regs.h
+++ b/target/linux/debug/imxregs/imx51regs.h
@@ -163,6 +163,28 @@ static struct reg_info regs[] =
 { "SACCST_2",	0x70014050, 0, 0xffffffff, 'x', "SSI2 AC97 Channel Status Register" },
 { "SACCEN_2",	0x70014054, 0, 0xffffffff, 'x', "SSI2 AC97 Channel Enable Register" },
 { "SACCDIS_2",	0x70014058, 0, 0xffffffff, 'x', "SSI2 AC97 Channel Disable Register" },
+/* IIM */
+{ "STAT",	0x83f98000, 0, 0xffffffff, 'x', "Status register" },
+{ "STATM",	0x83f98004, 0, 0xffffffff, 'x', "Status IRQ Mask register" },
+{ "ERR",	0x83f98008, 0, 0xffffffff, 'x', "Module Errors register" },
+{ "EMASK",	0x83f9800C, 0, 0xffffffff, 'x', "Error IRQ Mask register" },
+{ "FCTL",	0x83f98010, 0, 0xffffffff, 'x', "Fuse Control register" },
+{ "UA",		0x83f98014, 0, 0xffffffff, 'x', "Upper Address register" },
+{ "LA",		0x83f98018, 0, 0xffffffff, 'x', "Lower Address register" },
+{ "SDAT",	0x83f9801C, 0, 0xffffffff, 'x', "Explicit Sense Data register" },
+{ "PREV",	0x83f98020, 0, 0xffffffff, 'x', "Product Revision register" },
+{ "SREV",	0x83f98024, 0, 0xffffffff, 'x', "Silicon Revision register" },
+{ "PREG_P",	0x83f98028, 0, 0xffffffff, 'x', "Program Protection register" },
+{ "SCS0",	0x83f9802C, 0, 0xffffffff, 'x', "Software Controllable Signals register 0" },
+{ "SCS1",	0x83f98030, 0, 0xffffffff, 'x', "Software Controllable Volatile Hardware - Visible Signals register 1" },
+{ "SCS2",	0x83f98034, 0, 0xffffffff, 'x', "Software Controllable Volatile Hardware - Visible Signals register 2" },
+{ "SCS1",	0x83f98030, 0, 0xffffffff, 'x', "Software Controllable Volatile Hardware - Visible Signals register 3" },
+{ "SaharaEn0",	0x83f9803C, 0, 0xffffffff, 'x', "Software setting. Upon setting proper value allows SAHARA_EN blowing." },
+{ "SaharaEn1",	0x83f98040, 0, 0xffffffff, 'x', "Software setting. Upon setting proper value allows SAHARA_EN blowing." },
+{ "SaharaEn2",	0x83f98044, 0, 0xffffffff, 'x', "Software setting. Upon setting proper value allows SAHARA_EN blowing." },
+{ "SaharaEn3",	0x83f98048, 0, 0xffffffff, 'x', "Software setting. Upon setting proper value allows SAHARA_EN blowing." },
+{ "SaharaEn4",	0x83f9804C, 0, 0xffffffff, 'x', "Software setting. Upon setting proper value allows SAHARA_EN blowing." },
+{ "SaharaEn5",	0x83f98050, 0, 0xffffffff, 'x', "Software setting. Upon setting proper value allows SAHARA_EN blowing." },
 /* SSI 3 */
 { "STX0_3",	0x83fe8000, 0, 0xffffffff, 'x', "SSI3 Transmit Data Register 0" },
 { "STX1_3",	0x83fe8004, 0, 0xffffffff, 'x', "SSI3 Transmit Data Register 1" },


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