[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.0-2503-gef2bca9

[Fabien M <fa...@us...>]

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- Log -----------------------------------------------------------------
commit ef2bca95303ca795ad0498c2267cbf0683283930
Author: Fabien Marteau <fab...@ar...>
Date:   Wed Sep 21 10:50:46 2011 +0200

     Suppress useless end of lines under apf27-u-boot-2010.03.h file

commit bb754d79dc953f3114f497055320702963f89a6a
Author: Fabien Marteau <fab...@ar...>
Date:   Wed Sep 21 10:49:42 2011 +0200

    [uboot] Configure CS1 for fpga communication

-----------------------------------------------------------------------

Summary of changes:
 .../device/armadeus/apf27/apf27-u-boot-2010.03.h   |   24 ++++++++++----------
 1 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/buildroot/target/device/armadeus/apf27/apf27-u-boot-2010.03.h b/buildroot/target/device/armadeus/apf27/apf27-u-boot-2010.03.h
index a64f29e..805bf20 100644
--- a/buildroot/target/device/armadeus/apf27/apf27-u-boot-2010.03.h
+++ b/buildroot/target/device/armadeus/apf27/apf27-u-boot-2010.03.h
@@ -21,9 +21,9 @@
  *
  * 2008/08/19 Initial version based on apf9328 configuration file
  * 2008/10/09 Release 1.0 support u-boot 1.3.4
- * 2008/10/25 Release 1.1 added environment version 
- * 2008/11/01 Release 1.2 flash size independant 
- * 2008/11/09 Release 1.3 keep uboot partition locked & source clean-up 
+ * 2008/10/25 Release 1.1 added environment version
+ * 2008/11/01 Release 1.2 flash size independant
+ * 2008/11/09 Release 1.3 keep uboot partition locked & source clean-up
  * 2010/03/31 U-Boot 2010.03 migration. TODO merge mxc_i2c..
  */
 
@@ -534,7 +534,7 @@
 #define IMX27_NAND_16BITS	1
 #define NAND_MAX_CHIPS		1
 
-#define CONFIG_BOOT_TRACE_REG	0xAFFFFFF8 /* Addr to store traces of SPL boot */ 
+#define CONFIG_BOOT_TRACE_REG	0xAFFFFFF8 /* Addr to store traces of SPL boot */
 //#define NAND_ALLOW_ERASE_ALL
 //#define CONFIG_MTD_NAND_VERIFY_WRITE 1
 //#define CONFIG_SYS_NAND_SELECT_DEVICE  0	/* nand driver supports mutipl. chips */
@@ -714,8 +714,8 @@
 #define CONFIG_SYS_CS0L_VAL	0xa0330D01
 #define CONFIG_SYS_CS0A_VAL	0x00220800
 
-#define CONFIG_SYS_CS1U_VAL	0
-#define CONFIG_SYS_CS1L_VAL	0
+#define CONFIG_SYS_CS1U_VAL	0x00000f00
+#define CONFIG_SYS_CS1L_VAL	0x00000D01
 #define CONFIG_SYS_CS1A_VAL	0
 
 #define CONFIG_SYS_CS2U_VAL	0
@@ -735,7 +735,7 @@
 #define CONFIG_SYS_CS5L_VAL	0x00000D01
 #define CONFIG_SYS_CS5A_VAL	0
 
-#define CONFIG_SYS_EIM_VAL	0x00002000
+#define CONFIG_SYS_EIM_VAL	0x00002200
 
 /* FPGA specific settings */
 /* CLKO */
@@ -753,8 +753,8 @@
 /*
  * Default configuration for GPIOs and peripherals
  */
-#define CONFIG_SYS_DDIR_A_VAL		0x00000000  
-#define CONFIG_SYS_OCR1_A_VAL		0x00000000  
+#define CONFIG_SYS_DDIR_A_VAL		0x00000000
+#define CONFIG_SYS_OCR1_A_VAL		0x00000000
 #define CONFIG_SYS_OCR2_A_VAL		0x00000000
 #define CONFIG_SYS_ICFA1_A_VAL		0xFFFFFFFF
 #define CONFIG_SYS_ICFA2_A_VAL		0xFFFFFFFF
@@ -849,7 +849,7 @@
 /* LPDDR enable. latency hiding behavior enabled */
 //#define CONFIG_SYS_ESDMISC_VAL		ESDMISC_MA10_SHARE+ESDMISC_MDDREN
 /*
- * safe value in case of erratic crash during boot 
+ * safe value in case of erratic crash during boot
  *	(seen with some prototype boards)*/
 #define CONFIG_SYS_ESDMISC_VAL	ESDMISC_LHD+ESDMISC_MDDREN
 
@@ -860,8 +860,8 @@
 #define CONFIG_SYS_FMCR_VAL 0xFFFFFFFB
 #endif
 
-#define CONFIG_SYS_AIPI1_PSR0_VAL	0x20040304 
-#define CONFIG_SYS_AIPI1_PSR1_VAL	0xDFFBFCFB 
+#define CONFIG_SYS_AIPI1_PSR0_VAL	0x20040304
+#define CONFIG_SYS_AIPI1_PSR1_VAL	0xDFFBFCFB
 #define CONFIG_SYS_AIPI2_PSR0_VAL	0x00000000
 #define CONFIG_SYS_AIPI2_PSR1_VAL	0xFFFFFFFF
 


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