Introduction.md

ALCHA

The ALCHA project, including the language grammar and, by extension, this
wiki, is under development. This wiki serves as a documentation of the
project goals and aspirations, which are inherently unstable and subject to
change without notice.

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Table of Contents

• Introduction
• Automated Optimisation
• Source
• References
  • Similar Projects
  • Acknowledgements
  • Publications
  • Bibliography
• Lexical
• Grammar
• Modules
• Declarations
• Expressions
• Statements
• Arrays
• Functions
• Synchronous Circuits
• Classes
• Operator Overloading
• Scripting Features
• Advanced Attributes
• High-level Structures
• Simulation and Verification

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Introduction

ALCHA (architectural level computational hardware abstraction) is a command-line tool to generate vendor-specific FPGA projects from largely vendor-neutral text-based source code. The image below provides a rough overview of the intended tool-chain.

ALCHA is aimed at unifying the various aspects of FPGA firmware design (RTL design, finite state machines, timing and design constraints, as well as scripting) into a single language.

ALCHA is designed to be as portable, concise and expressive as possible, without the loss of low-level control. It provides a development platform that promises reduced development time and maintenance effort.

Automated Optimisation

The ALCHA compiler applies various optimisations before project synthesis, most of which are related to finite state machine resource usage. The details of this is outside the scope of this wiki. One notable optimisation, however, is automated multi-cycle analysis.

Unless specified otherwise, the circuit synthesis process assumes that all register-to-register paths have to have a delay of less than one clock period. This is not true for all paths in a typical state-machine. It is likely that a particular signal path have multiple clock-cycles in which to pass through the combinational cloud, thereby requiring less stringent timing constraints than the synthesis tool initially assumes.

Manually specifying multi-cycle paths is a labour-intensive and tedious process. ALCHA performs this task automatically whenever the design is compiled, thereby generating code that is easier to synthesise, resulting in reduced compilation times.

Source

The source is available from the git repository and GitHub.

References

Similar Projects

• Synflow Cx
• SpinalHDL
• CHISEL
• Migen
• MyHDL

Acknowledgements

Many of the ideas of ALCHA are borrowed from other existing languages. These include, among others:

• C++
• D
• 
• MATLAB
• Python

Publications

• J Taylor
  ALCHA - Architectural Level Computational Hardware Abstraction: A New Programming Language for FPGA Projects
  PhD thesis, University of Cape Town, Faculty of Engineering and the Built Environment, Department of Electrical Engineering, August 2022

• J Taylor and S Winberg
  ALCHA: An Alternative Programming Model for FPGA Firmware
  Proceedings of International Radar Conference, Boston, IEEE, April 2019

• J Taylor and S Winberg
  ALCHA: Introducing Arbitrary Fixed-point and Procedural Programming to FPGA Firmware Design
  Proceedings of International Workshop on Signal Processing Systems, IEEE, October 2018

• J Taylor and S Winberg
  ALCHA: New Object Oriented Approach to FPGA Project Development
  Proceedings of International Conference on Industrial Technology, IEEE, March 2016, Pages 707 – 712

Bibliography

• K Chapman
  Get your Priorities Right -- Make your Design Up to 50% Smaller
  Xilinx white paper, 2007

• K Chapman
  Get Smart About Reset: Think Local, Not Global
  Xilinx white paper, 2008

• P Coussy and A Morawiec
  High-Level Synthesis: from Algorithm to Digital Circuit
  Springer, 2008, ISBN 978-1-4020-8587-1, e-ISBN 978-1-4020-8588-8

• J DeLaere and S Zammattio
  Top 7 Reasons to Replace Your Microcontroller with a MAX 10 FPGA
  Altera, June 2015

• A Feller, R Noto and A M Smith
  Standard Cell Approach for Generating Custom CMOS/SOS Devices Using a Fully Automatic Layout Program
  IEEE Circuits and Systems Magazine, September 1981, Volume 3, Number 3, Pages 9 – 13

• L Fousse, G Hanrot, V Lefèvre, P Pélissier and P Zimmermann
  MPFR: A Multiple-precision Binary Floating-point Library with Correct Rounding
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• M Frigo and S G Johnson
  The Design and Implementation of FFTW3
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  2015, Version 6.1.0

• P Luksch, U Maier, S Rathmayer, M Weidmann, F Unger, P Bastian, V Reichenberger and A Haas
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• R Nane, V M Sima, C Pilato and J Choi
  A Survey and Evaluation of FPGA High-Level Synthesis Tools
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• R R Seban
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• J Stephenson
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• IEEE 1800-2012
  IEEE Standard for SystemVerilog – Unified Hardware Design, Specification, and Verification Language
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• T van Court and M C Herbordt
  Requirements for any HPC/FPGA Application Development Tool Flow
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• H Zheng, S T Gurumani, L Yang, D Chen and K Rupnow
  High-Level Synthesis with Behavioral-Level Multicycle Path Analysis
  Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, December 2014, Volume 33, Number 12, Pages 1832 – 1845

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