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...Native program execution is the only way for high-speed simulation. Full support for the 1987, 1993, 2002 versions of the IEEE 1076 VHDL standard, and partial for the 2008 and 2019 revisions. By using a code generator (LLVM, GCC or, x86_64/i386 only, a built-in one), it is much faster than any interpreted simulator. It can handle very large designs, such as leon3/grlib. GHDL runs on GNU/Linux, Windows and macOS; on x86, x86_64, armv6/armv7/aarch32, aarch64 and ppc64. You can freely download nightly assets, use OCI images (aka Docker/Podman containers), or try building it on your own machine.

Infra-red Remote Control Sampling using FPGA

The goal of this project is to implement a GameBoy in Verilog using the open source IceStorm tools for Lattice iCE40HX-8K FPGAs.

Convert C++ software programs into synthesisable Verilog using the Clang compiler frontend to parse and SystemC for intermediates.

CoreTML framework is an open-source template-based configuration system allowing the developer to create parametrized templates by inserting special content to any text files. Its main purpose is to serve as a toolkit for semiconductor IP core creation (based on VHDL/Verilog).

Module 1: durchblicker: embedded Logicanalyzer with direct output on VGA-monitor

Minimig is an open source FPGA Amiga chipset re-implementation created and designed by Dennis van Weeren - http://home.hetnet.nl/~weeren001/

vcd2svg can parse Value Change Dump (VCD) files and draw an impulse diagram using Scalable Vector Graphics (SVG). It works together with the GHDL open-source simulator.

A arcade snake game purely written in verilog [ no asm or C ]

A methodology to create netlists for printed circuit board layout using a novel PCB specific HDL as the source language.

This project includes a set of tools and guidelines designed for rapid production of large-scale embedded systems projects. The tools enable quick generation of reusable, reconfigurable hardware, using a user-specified hardware description language.

A verilog language compiler written using Java and JavaCC. It produces a netlist, an ascii text file, of all the cell connections. It can compile very large circuits comprised of many modules.

The project goal is to develop several IP cores that would implement artificial neural networks using FPGA resources. These cores will be designed in such a way to allow easy integration in the Xilinx EDK framework.

Genode FX is a composition of hardware and software components that enable the creation of fully fledged graphical user interfaces as system-on-chip solutions using commodity FPGAs such as Xilinx' Spartan3 and Virtex FPGAs.

The goal of this project is to develop an easily modifiable combination of VHDL firmware and LabView drivers for use with laboratory automation control and data acquisition using Terasic's DE2 board and the ISP1362 USB interface chip.

This project aims to generate video signal using an FPGA development board

This project aims to develop a colour-based vision processing system for use in RoboCup. We are using a CCD camera for input to an FPGA. The system locates coloured objects and outputs detected corners.

Software to support the JTAG bus (IEEE 1149.1). Primary purpose is for a JTAG programmer/debugger using FPGA's to provide ability to test and program JTAG devices.

The Affordable BIOS Restoration Tool provides VHDL and C code to recover from failed BIOS upgrades using affordable CPLD's. EEPROM's and Flash chips can be restored with this flash programmer. Interfaces for DIP and tsop packages are being developed.

Oscilloscope using a VGA monitor and a cpld

An FPGA based system, using captured video as source of a basketball movement. Human movement is detected and translated into motion vectors to hit a virtual ball.