Search Results for "drcom-for-linux" - Page 5

A VHDL - Verilog SAD256 module

Vaster is a EDA tool. It creates SystemC Cycle Accurate model from VerilogHDL RTL Model.

System on Chip design generator.

Yet Another DLX based Architecture System On a Chip (YADASOC) is a RTL Verilog implenetation of a DLX based CPU and subsystems.

SHELLEY Software HardwarE Light LanguagE Yep !

...The source code is available in the SVN repository: https://sourceforge.net/p/xrt/code/6/tree/trunk/ and consists in two folders: 1) /X-RT : A portable multiprocessor scheduling framework supporting scheduling periodic real-time tasks according to the G-EDF (Global Earliest Deadline First) scheduling platform. Current version supports major POSIX systems (Linux, QNX). 2) Hardware_GEDF_Scheduler: is a hardware implementation in VHDL (targeting FPGAs) of the G-EDF multiprocessor scheduling policy.

Tool-independent Makefile generator for VHDL models.

Picode is the ultimate VHDL picode 16 to 32 bits controller. It is described in only one entity and is implementable in standard FPGAs. It has it own compiler. Picode is designed to take only one or two clock cycle duration per instruction.

This project aim to develop a suite of tool to ease the development of ASIC/FPGA solution. The final program should be an IDE enabling the creation and specification of a project from it's start to finish.

Design and implementation of silicon and software for baseband processors conforming to IEEE wireless standards. Initial focus on WiMAX and WiFi.

Labcoat for SuperWikia Alpha fabrication manages new or revised fabrication processes. Its 'Cleanroom' applets allow codesmiths to access the lab environment, used to create semiconductors, substrate prototypes, chipset instruction blocks and other Labcoat projects. Our extensions in future releases will include UML support for C#/C++ conforming projects, import/export architecture schematics and refactoring sub-projects.