Search Results for "design automation"

Xschem is a schematic capture program, it allows to create a hierarchical representation of circuits with a top down approach . By focusing on interconnections, hierarchy and properties a complex system (IC) can be described in terms of simpler building blocks. A VHDL, Verilog or Spice netlist can be generated from the drawn schematic, allowing the simulation of the circuit. Key feature of the program is its drawing engine written in C and using directly the Xlib drawing primitives; this...

... with advance queries 8. Hierarchy Manipulation to create Power Domain, Voltage Domain, comply with Floor planning 8.a. Insert new hierarchy 8.b. Remove existing hierarchy 9. Associate the IP-XACT memory maps with the SoC component instances 10. Dump out the C Model for the entire design 11. Glue-Logic insertion 12. Spare port insertion across hierarchies 13. Automatic creation of the top module and it's ports based upon specified rule 14. Creates stub module

Smart GUI to create or update IP-XACT often needed for the IP packaging. It has capability create Bus Definitions from scratch to populate BusDef library. One can create IP-XACT Component, Design or Registers by importing Ip in System Verilog/Verilog-95/VHDL, instantiate Bus Interfaces with proper port maps and attributes as needed. Smart GUI to create IP-XACT Registers, Memory Maps, Address Blocks for IP- has feature to import XLS or Verilog . It has Tcl/Python API support...

Platform for advanced open source IP-Core development, i. e. dynamic memory controllers for FPGAs.

Capsim(r) C Text Mode Kernel(TMK),DSP and communication blocks, topologies, libraries and tools for the development of high performance block diagram digital signal processing and communications systems,built in interpreter for scripting.SystemC support.

openCarac aims to automatize the characterization of electronic circuits using your favourite Spice simulator and provide output files in HTML, LaTeX (c) and GNU Octave (c) scripts. openCarac is natively compatible with various simulators including: - Ngspice (c), http://ngspice.sourceforge.net - Gnucap (c), http://gnucap.org/dokuwiki/doku.php?id=gnucap:start - Xyce (c), http://xyce.sandia.gov It comes with an API which permits to add other features and extend openCarac...

QConsole is a custom Qt widget implementing a standard console to be inherited to support a specific scripting language or shell, and then embedded in any Qt application. As example, a Tcl console (QtclConsole) is provided for use in EDA applications

.../accounts/monitoring on this server. You are more than welcome to help (developing/deploying/design/administration/words of wisdom/whatever you think you can do) Project current status is: Initial stage - > Alpha, virtualbox image of the system, when show some stable and secure properties will be released as livecd aswell (vmdk on its way)

esweep is a scriptable audio measurement program which features various signals and signal processing functions. Its main purpose is the measurement of speakers.

Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory, combinational logic, FSM state/arc and assertion coverage report metrics viewable via GUI or ASCII format. This project is ported to github and can be found at: https://github.com/chiphackers/covered

Power format: CPF, UPF, xPF parsers, utilities and translators.

Efficient Symbolic Tools package (EST) is a BDD based tool for the formal verification of concurrent systems. Its advantages are flexibility, portability and an efficient memory management. It runs under different OS, including Linux and Windows 2000/XP.

decida is [de]vice & [ci]rcuit [d]ata [a]nalysis. It is used for electron device characterization, procedural simulation/analysis of electronic circuits, or more general data analysis tasks.

TkGate is a event driven digital circuit simulator with a tcl/tk-based graphical editor. TkGate supports a wide range of primitive circuit elements as well as user-defined modules for hierarchical design.

MMTL, the Multilayer Multiconductor Transmission Line 2-D and 2.5-D electromagnetic modeling tool suite, generates transmission parameters and SPICE models from descriptions of electronics interconnect dimensions and materials properties.

PEP is a modelling and verification framework for parallel systems, providing a large number of different modelling languages and verification techniques (e.g. SDL, Petri nets and model checking)

Scripting Tcl interface to Qt multiplatform library

IC CAD tools, documentation, scripts, and libraries for designing high-performance ICs, including SUE for schematics, MAX for layouts, DPC for datapaths and MCC for megacells. Prebuilt binaries for Linux, Sparc-Solaris, and HP-PA.

Spgmr08 is a Linux software package for programming devices in the Motorola MC68HC908 microcontroller family.

Icarus Verilog Interactive on MacOSX

a set of free tools and software aimed at design automation. SPICE ( NG-spice )MAGIC XCIRCUIT Main aim - to automate the layout of clock distribution on a chip, using rotary clock oscilation.

tkCybernetics is a small grafical tool for rapidly setting up simulations of simple cybernetic systems. It was designed for didactic purpose but might be useful for the quick test of some circuit too.

Source Navigator for Verilog is a verilog parser that allows Source Navigator to be used with the Verilog Hardware Description Language. http://sources.redhat.com/sourcenav

An online SSL (128-bit strong encryption) repository for scripts created and maintained by Synopsys Design Consultants.

Pure Tcl/Tk EDA Package. Schematic capture through to PCB layout. Has Part editor as well as editor for Schematic and PCB Decals.