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Showing 3 open source projects for "bridge hand generator"

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  • 1

    SmGen

    Verilog Finite State Machine (FSM) Code Generator

    SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing
    Downloads: 1 This Week
    Last Update:
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  • 2

    Handy TCP/IP Server/Client Tools

    Various TCP/IP servers, clients and network management tools

    IPtools is an all in one package that includes various TCP/IP tools. Server: - FTP - TFTP - Syslog - Web - Remote Command - General UDP server - Multicast server Client utilities: - Multicast client - TFTP client Starting on version 0.2.0, a powerful network connection tools UBridge is added, it can bridge: - VXLAN (newly released) - UDP sessions - NIC card of the PC - Connections to Cisco Router Simulator "GNS3/dynamips" and H3C Router Simulator...
    Downloads: 8 This Week
    Last Update:
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  • 3
    Linux Analysis Tool
    Program main objective - simplification of search and solution of the problems linked to operation of printers and their drivers in OS Linux. Project homepage: http://rm-rfv.blogspot.com/
    1 Review
    Downloads: 0 This Week
    Last Update:
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