Search Results for "altera"

...For the MSX it will be as if there is a magnetic disk drive with a real magnetic disk but for real it will be accessing a .dsk file inside a sdcard. Development tools used are: - Kicad version 2013-07-07 - Microchip XC8 v1.21 (free mode) - Micrchip MPLAB X IDE v1.90 - Altera´s Quartus Web Edition 11.0 UPDATE 2014-11-05 =============== Now it is working and the SVN repositories has it all: Schematics, PCB layout, firmware for the CPLD and the firmware for the MCU. But you have to download by your own the firmware for the 49F010 on the internet.

Altera Quartus creates .rpt files during synthesis, place&route and bitstream generation stages of FPGA project compilation. Verification engineer checks these reports, finds warning messages and put them into own report. But big projects can contain a lot of warnings, and manual warning search is very boring and long process. That's why this parsing tool was created.

...The VHDL model mimics the pipeline design described in Patterson & Hennessy's book (Computer Organisation and Design) and is an almost complete implementation of the MIPS32r2 instruction set. The TLB and assorted control registers will be included soon (as of fev 2015). The model was synthesized for an Altera EP4CE30F23. The model uses up 15% of combinational blocks and 5% logic registers.

ADopenPOWERLINK is an open source Ethernet Powerlink Controlled Node (Slave) solution using the Analog Devices ADSP-CM408F mixed signal processor (http://www.analog.com), along with Altera FPGA as network communication processor. The solution is based on openPOWERLINK provided by SYSTEC electronic (http://www.systec-electronic.com), B&R (http://www.br-automation.com) and Kalycito (http://www.kalycito.com). This release contains the necessary and required packages and documentation to setup the power-link controlled node using Analog Devices ADZS-CM408 EZLITE development board (http://www.analog.com/en/processors-dsp/cm4xx/adsp-cm408f/products/cm40x-ez/eb.html) as application processor, and a Terasic DE2-115 Altera FPGA development board as a communication processor.

we modify MicroC/OS-II to Multiple processors system

The ixo.de USB JTAG pod and firmware allows to access JTAG-capable chips via USB and a protocol like Altera USB-Blaster.

Script PHP para monitoramento de conexão com a internet, dispara um número X de pings contra N endereços IPs e/ou nomes, se a perda de pacotes for maior que um valor Y pode opcionalmente executar um script externo e no retorno do link executar outro.

This project implements a reduced instruction set (RISC) CPU in VHDL. It was designed for the Altera Flex10k20 chip, but the VHDL code should port to any compatable chip. The instruction set is extensive, and the design is easily extendable to 16 bits.

An operating system for an educational robot based on a Nios II board from Altera. Implemented in Nios II assember and C/C++.