Search Results for "cache memory simulator"

This is the stress-ng upstream project git repository. stress-ng will stress test a computer system in various selectable ways. It was designed to exercise various physical subsystems of a computer as well as the various operating system kernel interfaces. stress-ng was originally intended to make a machine work hard and trip hardware issues such as thermal overruns as well as operating system bugs that only occur when a system is being thrashed hard. Use stress-ng with caution as some of...

test-tlb is a tiny C microbenchmark that explores the performance characteristics of memory access patterns with respect to the CPU’s Translation Lookaside Buffer (TLB) and caches. It walks arrays using different strides and working-set sizes so you can observe when access patterns overflow cache or TLB capacity. By timing tight loops and varying parameters, the program reveals step-changes in latency that map to cache lines, page sizes, and TLB coverage.

DSPemu emule a digital signal processor TMS320F243, with console interface showing the registers and memory. With DSPemu is possible test algorithms such as Filter, FFT/IFFT. This can be integrate and used with a circuit simulator.