Search Results for "cache memory simulator"

Intel CMT CAT is a user-space software package providing support for Intel's Resource Director Technology (RDT). It offers tools and libraries to monitor and control cache allocation and memory bandwidth.​

Memcached is a high-performance, open-source distributed memory caching system, typically used to accelerate dynamic, database-driven websites by storing frequently accessed data in RAM. To build memcached on your machine from the local repo, you will have to install autotools, automake, and libevent. If you want TLS support, install OpenSSL's development packages and change the configure line. libseccomp (optional, experimental, Linux), enables process restrictions for better security....

This is the stress-ng upstream project git repository. stress-ng will stress test a computer system in various selectable ways. It was designed to exercise various physical subsystems of a computer as well as the various operating system kernel interfaces. stress-ng was originally intended to make a machine work hard and trip hardware issues such as thermal overruns as well as operating system bugs that only occur when a system is being thrashed hard. Use stress-ng with caution as some of...

The Twitter Image Pipeline is a streamlined framework for fetching and storing images in an application. The high-level concept is that all requests to fetch or store an image go through an image pipeline which encapsulates the work of checking the in-memory caches and an on disk cache before retrieving the image from over the network as well as keeping the caches both up to date and pruned. Twitter Image Pipeline came to fruition as numerous needs rose out of Twitter for iOS use cases. The system for image loading prior to TIP was fragile and inefficient with some severe edge cases. ...

test-tlb is a tiny C microbenchmark that explores the performance characteristics of memory access patterns with respect to the CPU’s Translation Lookaside Buffer (TLB) and caches. It walks arrays using different strides and working-set sizes so you can observe when access patterns overflow cache or TLB capacity. By timing tight loops and varying parameters, the program reveals step-changes in latency that map to cache lines, page sizes, and TLB coverage.

PerfCache is an API that allows for creation and management of a memory cache. It includes basic cache operations (insert and retrieve), replacement policies, and expiration. Cache entry keys are strings of bytes, and data items are arrays of bytes. Variable length keys and data are supported. The cache itself is implemented as an array. The cache infrastructure includes a directory, mapping cache entry keys to cache array indices, and a sub-system for handling cache entry replacement metadata. ...

DSPemu emule a digital signal processor TMS320F243, with console interface showing the registers and memory. With DSPemu is possible test algorithms such as Filter, FFT/IFFT. This can be integrate and used with a circuit simulator.

Origin is a evolver for the programming game Corewars. Part of this project is a modified MARS (Memory Array Redcode Simulator) written in C especialy for evolvers. With SWIG its going to be very easy to use in different languages.