Search Results for "risc"
Sort By:
Showing 34 open source projects for "risc"
View related business solutions-
AI-generated apps that pass security reviewRetool lets you generate dashboards, admin panels, and workflows directly on your data. Type something like “Build me a revenue dashboard on my Stripe data” and get a working app with security, permissions, and compliance built in from day one. Whether on our cloud or self-hosted, create the internal software your team needs without compromising enterprise standards or control.
-
Find Hidden Risks in Windows Task SchedulerWindows Task Scheduler might be hiding critical failures. Download the free JAMS diagnostic tool to uncover problems before they impact production—get a color-coded risk report with clear remediation steps in minutes.
-
1
Chipyard
An Agile RISC-V SoC Design Framework with in-order cores
Chipyard is a framework and generator for constructing custom RISC‑V SoC hardware. Built at UC Berkeley, it leverages Chisel/FIRRTL to generate full-stack systems—from CPU cores to peripherals—and includes simulators, FPGA deployment tools, and integration with Rocket Chip and other RISC‑V ecosystems. -
2
riscv-isa-manual
RISC-V Instruction Set Manual
This repository contains the source files for the official RISC‑V Instruction Set Manual, including the Privileged RISC‑V Manual in LaTeX and the Unprivileged Manual in AsciiDoc. It tracks formal ratified versions of the ISA maintained by RISC‑V International and hosts build workflows for releasing updated ISA documents. -
3
XiangShan
Open-source high-performance RISC-V processor
XiangShan is an open-source, high-performance RISC-V processor project that implements out-of-order superscalar cores using Chisel for hardware construction. The design targets modern performance goals—deep pipelines, speculative execution, multi-issue decode/execute, and sophisticated branch prediction—while remaining synthesizable for ASIC flows and portable to FPGAs for research. -
4
tinygrad
Deep learning framework
...Due to its extreme simplicity, it aims to be the easiest framework to add new accelerators to, with support for both inference and training. If XLA is CISC, tinygrad is RISC. -
Atera all-in-one platform IT management software with AI agentsAtera’s AI agents don’t just assist, they act. From detection to resolution, they handle incidents and requests instantly, taking your IT management from automated to autonomous.
-
5
XNNPACK
High-efficiency floating-point neural network inference operators
XNNPACK is a highly optimized, low-level neural network inference library developed by Google for accelerating deep learning workloads across a variety of hardware architectures, including ARM, x86, WebAssembly, and RISC-V. Rather than serving as a standalone ML framework, XNNPACK provides high-performance computational primitives—such as convolutions, pooling, activation functions, and arithmetic operations—that are integrated into higher-level frameworks like TensorFlow Lite, PyTorch Mobile, ONNX Runtime, TensorFlow.js, and MediaPipe. The library is written in C/C++ and designed for maximum portability, efficiency, and performance, leveraging platform-specific instruction sets (e.g., NEON, AVX, SIMD) for optimized execution. ... -
6
BSC
Bluespec Compiler (BSC)
...The ecosystem includes standard libraries, FIFOs, interfaces, and utilities that encourage reuse and clean separation of datapaths and control. By raising the abstraction for hardware architecture while preserving efficient output, BSC helps teams explore complex designs—such as RISC-V cores or accelerators—more productively. -
7
stress-ng
This is the stress-ng upstream project git repository.
This is the stress-ng upstream project git repository. stress-ng will stress test a computer system in various selectable ways. It was designed to exercise various physical subsystems of a computer as well as the various operating system kernel interfaces. stress-ng was originally intended to make a machine work hard and trip hardware issues such as thermal overruns as well as operating system bugs that only occur when a system is being thrashed hard. Use stress-ng with caution as some of... -
8
Unicorn Engine
Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc
Unicorn is a lightweight multi-platform, multi-architecture CPU emulator framework. Highlight features. Multi-architectures: ARM, ARM64 (ARMv8), m68k, MIPS, PowerPC, RISC-V, S390x (SystemZ), SPARC, TriCore & x86 (include x86_64). Clean/simple/lightweight/intuitive architecture-neutral API. Implemented in pure C language, with bindings for Pharo, Crystal, Clojure, Visual Basic, Perl, Rust, Haskell, Ruby, Python, Java, Go, D, Lua, JavaScript, .NET, Delphi/Pascal & MSVC available. Native support for Windows & *nix (with macOS, Linux, Android, *BSD & Solaris confirmed). ... -
9
Halide
A language for fast, portable data-parallel computation
Halide is a programming language for fast, portable data-parallel computation. It was designed to make writing high-performance image and array processing code much easier on modern machines. It works on all major operating systems and with several CPU architectures (X86, ARM, MIPS, Hexagon, PowerPC) and GPU Compute APIs (CUDA, OpenCL, OpenGL, among others). It isn't a standalone programming language however; rather it is embedded in C++ which means that you write C++ code, building an... -
Yeastar: Business Phone System and Unified CommunicationsUser-friendly, optimized, and scalable, the Yeastar P-Series Phone System redefines business connectivity by bringing together calling, meetings, omnichannel messaging, and integrations in one simple platform—removing the limitations of distance, platforms, and systems.
-
10
oneDNN
oneAPI Deep Neural Network Library (oneDNN)
...The library is optimized for Intel(R) Architecture Processors, Intel Processor Graphics and Xe Architecture graphics. oneDNN has experimental support for the following architectures: Arm* 64-bit Architecture (AArch64), NVIDIA* GPU, OpenPOWER* Power ISA (PPC64), IBMz* (s390x), and RISC-V. oneDNN is intended for deep learning applications and framework developers interested in improving application performance on Intel CPUs and GPUs. Deep learning practitioners should use one of the applications enabled with oneDNN. -
11
Unikraft
A next-generation cloud native kernel designed to unlock performance
Unikraft powers the next generation of cloud-native, containerless applications by enabling you to radically customize and build custom OS/kernels; unlocking best-in-class performance, security primitives, and efficiency savings. Unikraft optimizes resource utilization, leading to smaller footprints (meaning higher server saturation) and improved efficiency in resource-constrained environments. Unikraft is an open-source project driven by a vibrant community of over 100 developers, fostering... -
12
WinAVR (tm) is a suite of executable, open source software development tools for the Atmel AVR series of RISC microprocessors hosted on the Windows platform. Includes the GNU GCC compiler for C and C++.
-
13
ACME Cross-Assembler
multi-platform cross assembler for 6502/6510/65816 cpu
ACME is a free cross assembler released under the GNU GPL. It can produce code for the following processors: 6502, 6510 (including illegal opcodes), 65c02 and 65816. ACME supports the standard assembler stuff like global/local/anonymous labels, offset assembly, conditional assembly and looping assembly. It can include other source files as well as binaries while assembling. Calculations can be done in integer or float mode. Oh, and it is fast. -
14
Mecrisp - A family of optimising native code Forth implementations for MSP430, ARM Cortex M, RISC-V RV32IM(C), MIPS M4K and FPGAs.
-
15
CRC RevEng
Arbitrary-precision CRC calculator and algorithm finder
CRC RevEng is a portable, arbitrary-precision CRC calculator and algorithm finder. It calculates CRCs using any of the 113 preset algorithms, or a user-specified algorithm to any width. It calculates reversed CRCs to give the bit pattern that produces a desired forward CRC. CRC RevEng also reverse-engineers any CRC algorithm from sufficient correctly formatted message-CRC pairs and optional known parameters. It comprises powerful input interpretation options. Compliant with Ross Williams'... -
16
Decompiler
Binary executable decompiler
Reko decompiler reads program binaries, decompiles them, infers data types, and emits structured C source code. Designed with a pluggable architecture, it currently has: - support for 68k, ARM, MIPS, PowerPC, Risc-V, Sparc, x86, Z80 processors and many more - support for EXE, Elf, AmigaOS Hunk executable formats and many more - support for MS-DOS, Win32, U*ix, AmigaOS , C64, ZX-81 Reko decompiler comes with a GUI and a command-line interface. Visit https://github.com/uxmal/reko for the GIT repository. -
17
amforth: Interpreter on Microcontrollers
amforth is an extendible interpreter on microcontrollers
amforth is an extendable command interpreter running on AVR ATmega and TI MSP430 microcontrollers. The Risc-V and ARM architectures are ascending. Turnkey actions for IoT workloads are possible as well. The command language is close to the Forth 2012 standard. -
18
UniSIMD-assembler
SIMD macro assembler unified for ARM, MIPS, PPC and x86
UniSIMD assembler is a high-level C/C++ macro assembler framework unified across ARM, MIPS, POWER and x86 architectures. It establishes a subset of both BASE and SIMD instruction sets with clearly defined common API, so that application logic can be written and maintained in one place without code replication. The assembler itself isn't a separate tool, but rather a collection of C/C++ header files, which applications need to include directly in order to use. At present, Intel... -
19
CrossBrowdy
JavaScript framework to build game engines, games, emulators and apps
CrossBrowdy is a free and open-source JavaScript framework that allows to create multimedia apps, emulators, game engines and games that will be compatible with any device. Any software developed with CrossBrowdy should be able to be used in any JavaScript compatible web client (including browser plug-in, add-on, extension, app...) which supports "document.getElementById". This framework allows any developer to manage easier many different things, such as audio (with Flash fallback,... -
20
RARS
RISC-V Assembler and Runtime Simulator
RARS, the RISC-V Assembler, Simulator, and Runtime, will assemble and simulate the execution of RISC-V assembly language programs. Its primary goal is to be an effective development environment for people getting started with RISC-V. -
21
Selfie
An educational software system of a tiny self-compiling C compiler
An educational software system of a tiny self-compiling C compiler, a tiny self-executing RISC-V emulator, and a tiny self-hosting RISC-V hypervisor. Selfie is a project of the Computational Systems Group at the Department of Computer Sciences of the University of Salzburg in Austria. The Selfie Project provides an educational platform for teaching undergraduate and graduate students the design and implementation of programming languages and runtime systems. -
22
Rocket Chip
Rocket Chip Generator
Rocket Chip is a parameterized RISC-V SoC generator written in Chisel that produces synthesizable RTL for a wide range of cores and configurations. At its heart is the Rocket core, a simple, in-order, five-stage RISC-V implementation, but the generator composes much more: coherent caches, MMUs, interrupt controllers, and buses via the TileLink interconnect. A diplomacy framework (LazyModules) lets designers wire components with negotiated parameters, enabling reuse and rapid exploration of different cache sizes, port counts, and memory hierarchies. ... -
23
Bareflank Hypervisor
lightweight hypervisor SDK written in C++
The Bareflank Hypervisor is an open source hypervisor Software Development Toolkit (SDK) for Rust and C++, led by Assured Information Security, Inc. (AIS), that provides the tools needed to rapidly prototype and create your own hypervisor on 64bit versions of Intel and AMD (ARMv8 CPUs, RISC-V and PowerPC also planned). The Bareflank SDK is intended for instructional/research purposes as it only provides enough virtualization support to start/stop a hypervisor. Bareflank can also be used as the foundation to create your own, fully functional hypervisor as it uses the MIT license, and includes 100% unit test coverage and compliance for AUTOSAR. ... -
24
RISC-V BOOM
SonicBOOM: The Berkeley Out-of-Order Machine
The riscv-boom project (also called BOOM or SonicBOOM) implements a high-performance, synthesizable out-of-order RISC-V core written in the Chisel hardware construction language. It targets the RV64GC (i.e. 64-bit with general + compressed + floating point) instruction set and supports features such as virtual memory, caches, atomics, and IEEE-754 floating point. The design is parameterizable, meaning users can tune pipeline widths, buffer sizes, functional units, and other microarchitectural knobs to explore tradeoffs. ... -
25
jMIPS
MIPS processor in Java
A MIPS processor modeled in Java for educational purposes and aimed at undergraduate Computer Architecture courses. It presently runs MIPS 32-bit R3000 ELF executables on any platform where Java itself will run. Five successively more sophisticated models of a pipelined MIPS RISC processor are included. Though the code is deliberately kept clear and simple in order that readers are able to figure out how a real processor works through the medium of the code, it will soon be able to run a real Linux O/S kernel compiled for MIPS in Java - at what speed we don't know!
