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SIMD macro assembler unified across ARM, MIPS, Power and x86

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UniSIMD assembler is a high-level C/C++ macro assembler framework unified across
ARM, MIPS, Power and x86 architectures. It establishes a subset of both BASE and
SIMD instruction sets with clearly defined common API, so that application logic
can be written and maintained in one place without code replication.
The assembler itself isn't a separate tool, but rather a collection of C/C++
header files, which applications need to include directly in order to use.

At present, Intel SSE/SSE2/SSE4 and AVX/AVX2/AVX-512 (32/64-bit x86 ISAs),
ARMv7 NEON/NEONv2, ARMv8:AArch32 NEON and AArch64 NEON (32/64-bit ARM ISAs),
MIPS 32/64-bit r5/r6 MSA and Power 32/64-bit VMX/VSX (little/big-endian ISAs)
are mostly implemented, although scalar SIMD subset, horizontal SIMD reductions,
wider SIMD vectors with zeroing/merging predicates in 3/4-operand instructions,
larger register files and other architectures are planned as future extensions.

See README file.

UniSIMD-assembler Web Site




MIT License


  • Unified, Universal, Portable, Compatible code
  • Explicit register-allocation, predictable performance
  • SIMD-aligned backend structures with offsets/factors
  • Vector-length-agnostic vertical SIMD ISA
  • C/C++, Compute, SPMD on 4 major archs
  • Intel SSE/SSE2/SSE4 and AVX/AVX2/AVX-512
  • ARM NEON, ARMv8 AArch32, AArch64 NEON
  • MIPS r5/r6 MSA (Warrior P5600, I6400/P6600)
  • Power VMX/VSX (PowerPC G4, POWER7/8)
  • CISC, RISC, CISC on RISC, little/big-endian ISA
  • 64/32-bit hybrid mode for native 64-bit ABI
  • Full 64-bit addressing for BASE and SIMD
  • 32/64-bit configurable SIMD elements (fp+int)
  • Potential for bit-exact fp-compute across targets
  • Used in QuadRay-engine


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Additional Project Details

Intended Audience


Programming Language

C++, Assembly, C



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