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ALCHA aims to reduce FPGAproject develop time by means of automation and abstraction, but without loosing the low-level control that HDLs, such as Verilog, provides.
It will support an object oriented programming model, abstract data and signal types, and compile-time scripting.
Demo of Simulink to C++ C or HDL FGA for HFT potential
Video and files download for Visual trading idea to C++ or FPGA HFT Meetup
File download sample: test model (Matlab 2014b with Visual Studio 2013 C++ project generated)
Powerpoint MATLAB SIMULINK
http://quantlabs.net/blog/2015/04/video-and-files-download-for-visual-trading-idea-to-c-or-fpga-hft-meetup/
Writing Testbenches for FPGA/ASIC design is always a very fastidious and boring task.
This project helps any FPGA/ASIC designer by providing a full RTL test environment with C support.
This project aim to develop a suite of tool to ease the development of ASIC/FPGA solution. The final program should be an IDE enabling the creation and specification of a project from it's start to finish.